Keyword : skew


Adaptive Scanline Filling Algorithm for OpenVG 2D Vector Graphics Accelerator
Daewoong KIM Kilhyung CHA Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/07/01
Vol. E92-D  No. 7 ; pp. 1500-1502
Type of Manuscript:  LETTER
Category: Computer Graphics
Keyword: 
OpenVGtwo-dimensional vector graphicsadaptivescanline fillingscanning directionskew
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Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis
Takayuki OBATA Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3585-3595
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high level synthesisRT datapathskewwiring delayscheduling
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Power and Skew Aware Point Diffusion Clock Network
Gunok JUNG Chunghee KIM Kyoungkuk CHAE Giho PARK Sung Bae PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/11/01
Vol. E91-C  No. 11 ; pp. 1832-1834
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
clock networkskewlatencylow power
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A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications
Hidehiro TOYODA Shinji NISHIMURA Michitaka OKUNO Matsuaki TERADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 1957-1963
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Architecture for Communication/Server Systems
Keyword: 
EthernetVSRbackplaneskewFECFire codes
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All-Digital Clock Deskew Buffer with Variable Duty Cycles
Shao-Ku KAO Shen-Iuan LIU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 753-760
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
skewduty cyclepulsewidth detectortime-to-digital conversion
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100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet
Hidehiro TOYODA Shinji NISHIMURA Michitaka OKUNO Kouji FUKUDA Kouji NAKAHARA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/03/01
Vol. E89-B  No. 3 ; pp. 696-703
Type of Manuscript:  Special Section PAPER (Special Section on the Next Generation Ethernet Technologies)
Category: 
Keyword: 
EthernetMANskewFEC
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Skew Detection and Reconstruction of Color-Printed Document Images
Yi-Kai CHEN Jhing-Fa WANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/08/01
Vol. E84-D  No. 8 ; pp. 1018-1024
Type of Manuscript:  Special Section PAPER (Special Issue on Image Recognition and Understanding)
Category: 
Keyword: 
color-printed document imageskewcolor-transition countOCR
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Skew-Compensation Technique for Parallel Optical Interconnections
Takeshi SAKAMOTO Nobuyuki TANAKA Yasuhiro ANDO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/08/25
Vol. E82-C  No. 8 ; pp. 1428-1434
Type of Manuscript:  Special Section PAPER (Joint Special Issue on Recent Progress in Optoelectronics and Communications)
Category: Optical Systems and Technologies
Keyword: 
parallel optical interconnectionskewskew compensationframe codeframe synchronizationbit synchronization
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Skew-Compensation Technique for Parallel Optical Interconnections
Takeshi SAKAMOTO Nobuyuki TANAKA Yasuhiro ANDO 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1999/08/25
Vol. E82-B  No. 8 ; pp. 1162-1168
Type of Manuscript:  Special Section PAPER (Joint Special Issue on Recent Progress in Optoelectronics and Communications)
Category: Optical Systems and Technologies
Keyword: 
parallel optical interconnectionskewskew compensationframe codeframe synchronizationbit synchronization
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A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz
Hiroki SUTOH Kimihiro YAMAKOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C  No. 7 ; pp. 1334-1340
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLLCMOS/SIMOXVCOclockjitterskewlock range
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Delay and Skew Minimized Clock Tree Synthesis for Embedded Arrays
Midori TAKANO Fumihiro MINAMI Naohito KOJIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10 ; pp. 1405-1409
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword: 
clock routingdelayskewembedded array
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