Keyword : single-electron transistor (SET)


A Simulation Methodology for Single-Electron Multiple-Valued Logics and Its Application to a Latched Parallel Counter
Hiroshi INOKAWA Yasuo TAKAHASHI Katsuhiko DEGAWA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1818-1826
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
single-electron transistor (SET)multiple-valued logic (MVL)counteranalytical modelSPICE
 Summary | Full Text:PDF