Keyword : single event upset

Simulation-Based Understanding of “Charge-Sharing Phenomenon” Induced by Heavy-Ion Incident on a 65nm Bulk CMOS Memory Circuit
Akifumi MARU Akifumi MATSUDA Satoshi KUBOYAMA Mamoru YOSHIMOTO 
Publication:   
Publication Date: 2022/01/01
Vol. E105-C  No. 1 ; pp. 47-50
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
single event upset, charge sharing, device simulation, 65 nm bulk CMOS memory, 
 Summary | Full Text:PDF
Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path
Go MATSUKAWA Yuta KIMI Shuhei YOSHIDA Shintaro IZUMI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/06/01
Vol. E99-A  No. 6 ; pp. 1198-1205
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
single event effect, single event upset, soft error propagation, logical masking, temporal masking, 
 Summary | Full Text:PDF
A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology
Aibin YAN Huaguo LIANG Zhengfeng HUANG Cuiyun JIANG Maoxiang YI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/12/01
Vol. E98-C  No. 12 ; pp. 1171-1178
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
transient fault, single event upset, soft error, radiation hardening, circuit reliability, 
 Summary | Full Text:PDF
Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments
Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4 ; pp. 518-527
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
self synchronous, gate-level, robustness, single event upset, low voltage, reliability, 
 Summary | Full Text:PDF
A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis
Takashi IMAGAWA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4 ; pp. 454-462
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
soft error, single event upset, triple modular redundancy, reliability, simulated annealing, 
 Summary | Full Text:PDF
DFV-Aware Flip-Flops Using C-Elements
Changnoh YOON Youngmin CHO Jinsang KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/07/01
Vol. E94-C  No. 7 ; pp. 1229-1232
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
design-for-variability, flip-flop, nanometer process, PVT variation, single event upset, 
 Summary | Full Text:PDF
On Synthesizing a Reliable Multiprocessor for Embedded Systems
Makoto SUGIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2560-2569
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
heterogeneous multiprocessor synthesis, soft error, single event upset, reliability, real-time system, 
 Summary | Full Text:PDF
Reliability Inherent in Heterogeneous Multiprocessor Systems and Task Scheduling for Ameliorating Their Reliability
Makoto SUGIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 1121-1128
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
soft error, single event upset, reliability, task scheduling, heterogeneous multiprocessor systems, 
 Summary | Full Text:PDF
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems
Makoto SUGIHARA Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 410-417
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
single event upset, SRAM, DRAM, reliability, cache architecture, task scheduling, 
 Summary | Full Text:PDF
Temperature Dependence of Single Event Charge Collection in SOI MOSFETs by Simulation Approach
Tsukasa OOOKA Hideyuki IWATA Takashi OHZONE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/03/25
Vol. E80-C  No. 3 ; pp. 417-422
Type of Manuscript:  Special Section PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: 
Keyword: 
SOI MOSFETs, numerical simulation, temperature dependence, single event upset, soft errors, 
 Summary | Full Text:PDF