IEICE Trans

Keyword : signal integrity

Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity Akira TSUCHIYA Akitaka HIRATSUKA Toshiyuki INOUE Keiji KISHINE Hidetoshi ONODERA
Publication: Publication Date: 2019/07/01 Vol. E102-C No. 7 ; pp. 573-579 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Keyword: power integrity, signal integrity, multi-layered inductor,
	Summary \| Full Text:PDF

Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction Masahiro KANO Toru NAKURA Tetsuya IIZUKA Kunihiro ASADA
Publication: Publication Date: 2018/04/01 Vol. E101-C No. 4 ; pp. 292-298 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: signal integrity, resonant power supply noise, triangular active charge injection, DLL, vernier TDC,
	Summary \| Full Text:PDF

Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking Satoshi TAKAYA Hiroaki IKEDA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/06/01 Vol. E97-C No. 6 ; pp. 557-565 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: wide I/O bus, through silicon via, signal integrity, power integrity,
	Summary \| Full Text:PDF

Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint Mikiko SODE TANAKA Nozomu TOGAWA Masao YANAGISAWA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 ; pp. 2482-2489 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power supply noise, power distribution network, signal integrity, circuit simulation,
	Summary \| Full Text:PDF

Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint Mikiko SODE TANAKA Nozomu TOGAWA Masao YANAGISAWA Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/04/01 Vol. E94-A No. 4 ; pp. 1082-1090 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: power supply noise, power distribution networks, signal integrity, circuit simulation,
	Summary \| Full Text:PDF

Analysis of Microstrip Line with Bends Using Fourier Transform and Mode-Matching Technique Hyun Ho PARK
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2010/07/01 Vol. E93-B No. 7 ; pp. 1731-1738 Type of Manuscript: Special Section PAPER (Special Section on Advanced Electromagnetic Compatibility Technology in Conjunction with Main Topics of EMC'09/Kyoto) Category: PCB and Circuit Design for EMI Control Keyword: microstrip bend, electromagnetic scattering, signal integrity, Fourier transform, mode-matching technique,
	Summary \| Full Text:PDF

An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology Tetsuro MATSUNO Daisuke FUJIMOTO Daisuke KOSAKA Naoyuki HAMANISHI Ken TANABE Masazumi SHIOCHI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 ; pp. 820-826 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: noise emulation, substrate noise, power supply noise, signal integrity, substrate coupling, power integrity,
	Summary \| Full Text:PDF

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails Takushi HASHIDA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 ; pp. 842-848 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: power-line communication, on-chip diagnosis, signal integrity, power integrity, mixed-signal circuit,
	Summary \| Full Text:PDF

Compact CAD Models for the Signal Integrity Verification of Multi-Coupled Transmission Lines Hyunsik KIM Yungseon EO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/04/01 Vol. E93-A No. 4 ; pp. 752-760 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: crosstalk, multi-coupled transmission lines, signal integrity, signal transient, simulation,
	Summary \| Full Text:PDF

Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits Tetsuro MATSUNO Daisuke KOSAKA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/02/01 Vol. E93-A No. 2 ; pp. 440-447 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: substrate noise, power supply noise, signal integrity, substrate coupling, power integrity,
	Summary \| Full Text:PDF

Analytical Solution for Two Parallel Traces on PCB in the Time Domain with Application to Hairpin Delay Lines Fengchao XIAO Kimitoshi MURANO Yoshio KAMI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2009/06/01 Vol. E92-B No. 6 ; pp. 1953-1959 Type of Manuscript: Special Section PAPER (Special Section on 3rd Pan-Pacific EMC Joint Meeting -- PPEMC'08--) Category: Keyword: crosstalk, serpentine, meander, delay, mode decomposition, telegrapher's equations, signal integrity, time-domain transmission,
	Summary \| Full Text:PDF

Simultaneous Switching Noise Analysis for High-Speed Interface Narimasa TAKAHASHI Kenji KAGAWA Yutaka HONDA Yo TAKAHASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 ; pp. 460-467 Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era) Category: Keyword: SSN, power integrity, signal integrity, DDR,
	Summary \| Full Text:PDF

Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation Masatomo MIURA Takahiro HANYU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 ; pp. 589-594 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: crosstalk, signal integrity, differential-pair circuit, multiple-valued logic,
	Summary \| Full Text:PDF

Redundant Vias Insertion for Performance Enhancement in 3D ICs Xu ZHANG Xiaohong JIANG Susumu HORIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 ; pp. 571-580 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: 3D IC, redundant vias, via placement, delay, signal integrity, impedance matching,
	Summary \| Full Text:PDF

Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements Kouji ICHIKAWA Yuki TAKAHASHI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/06/01 Vol. E90-C No. 6 ; pp. 1282-1290 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: large scale integration, electro magnetic interference, printed circuit board, signal integrity, power supply integrity, integrated analysis,
	Summary \| Full Text:PDF

Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect Yasuhiro OGASAHARA Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/04/01 Vol. E90-A No. 4 ; pp. 724-731 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: signal integrity, interconnect delay, capacitive crosstalk, inductive crosstalk,
	Summary \| Full Text:PDF

Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise Mitsuya FUKAZAWA Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 ; pp. 1559-1566 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: delay variation, dynamic power supply noise, static IR drop, on-chip waveform monitor circuit, signal integrity,
	Summary \| Full Text:PDF

An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity Koichiro NOGUCHI Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/06/01 Vol. E89-C No. 6 ; pp. 761-768 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: Keyword: signal integrity, substrate crosstalk, delay variation, on-chip monitor,
	Summary \| Full Text:PDF

An Enhanced Time-Domain Circuit Simulation Technique Based on LIM Hidemasa KUBOTA Yuichi TANJI Takayuki WATANABE Hideki ASAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/05/01 Vol. E89-A No. 5 ; pp. 1505-1506 Type of Manuscript: LETTER Category: Numerical Analysis and Optimization Keyword: circuit simulation, LIM, numerical integration, power integrity, signal integrity,
	Summary \| Full Text:PDF

Band-Stop Filter Effect of Power/Ground Plane on Through-Hole Signal Via in Multilayer PCB Jun So PAK Masahiro AOYAGI Katsuya KIKUCHI Joungho KIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/04/01 Vol. E89-C No. 4 ; pp. 551-559 Type of Manuscript: PAPER Category: Electronic Components Keyword: power/ground plane, signal via, return current, signal integrity, power integrity, radiated emission,
	Summary \| Full Text:PDF

Trends of On-Chip Interconnects in Deep Sub-Micron VLSI Danardono Dwi ANTONO Kenichi INAGAKI Hiroshi KAWAGUCHI Takayasu SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 ; pp. 392-394 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Interconnect Technique Keyword: on-chip interconnects, deep sub-micron, inductive effect, signal integrity,
	Summary \| Full Text:PDF

Linear and Nonlinear Macromodels for System-Level Signal Integrity and EMC Assessment Flavio CANAVERO Stefano GRIVET-TALOCIA Ivan A. MAIO Igor S. STIEVANO
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2005/08/01 Vol. E88-B No. 8 ; pp. 3121-3126 Type of Manuscript: INVITED PAPER (Special Section of 2004 International Symposium on Electromagnetic Compatibility) Category: Keyword: signal integrity, electromagnetic compatibility, macromodeling, digital integrated circuits, transmission lines, 3D interconnects, passivity,
	Summary \| Full Text:PDF

Efficient False Aggressors Pruning with Functional Correlation Hyungwoo LEE Juho KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 ; pp. 3159-3165 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: signal integrity, false aggressor, crosstalk, timing analysis,
	Summary \| Full Text:PDF

Sparse Realization of Passive Reduced-Order Interconnect Models via PRIMA Yuya MATSUMOTO Yuichi TANJI Mamoru TANAKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/01/01 Vol. E87-A No. 1 ; pp. 251-257 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: signal integrity, interconnects, passive reduced-order models, PRIMA, SPICE,
	Summary \| Full Text:PDF

Crosstalk Noise Estimation for Generic RC Trees Masanori HASHIMOTO Masao TAKAHASHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 2965-2973 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: crosstalk noise, capacitive coupling, noise estimation, signal integrity,
	Summary \| Full Text:PDF

Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays Sadahiro TANI Yoshihiro UCHIDA Makoto FURUIE Shuji TSUKIYAMA BuYeol LEE Shuji NISHI Yasushi KUBOTA Isao SHIRAKAWA Shigeki IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 2923-2932 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: interconnect, LCD, parasitic capacitance, signal integrity, circuit simulation,
	Summary \| Full Text:PDF

Routing Methodology for Minimizing Crosstalk in SoC Takashi YAMADA Atsushi SAKAI Yoshifumi MATSUSHITA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/09/01 Vol. E86-A No. 9 ; pp. 2347-2356 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: SoC, signal integrity, crosstalk, interconnect, timing analysis,
	Summary \| Full Text:PDF

Measurement-Based Line Parameter Extraction Method for Multiple-Coupled Lines in Printed Circuit Boards Yong-Ju KIM Han-Sub YOON Gyu MOON Seongsoo LEE Jae-Kyung WEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/08/01 Vol. E86-C No. 8 ; pp. 1649-1656 Type of Manuscript: Special Section PAPER (Special Issue on Microwave and Millimeter Wave Technology) Category: Keyword: crosstalk noise, signal integrity, line parameter extraction method,
	Summary \| Full Text:PDF

Signal Integrity Design and Analysis for a 400 MHz RISC Microcontroller Akira YAMADA Yasuhiro NUNOMURA Hiroaki SUZUKI Hisakazu SATO Niichi ITOH Tetsuya KAGEMOTO Hironobu ITO Takashi KURAFUJI Nobuharu YOSHIOKA Jingo NAKANISHI Hiromi NOTANI Rei AKIYAMA Atsushi IWABU Tadao YAMANAKA Hidehiro TAKATA Takeshi SHIBAGAKI Takahiko ARAKAWA Hiroshi MAKINO Osamu TOMISAWA Shuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 ; pp. 635-642 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Design Methods and Implementation Keyword: microcontroller, high-speed, signal integrity, IR drop, design technique,
	Summary \| Full Text:PDF

Non-uniform Multi-Layer IC Interconnect Transmission Line Characterization for Fast Signal Transient Simulation of High-Speed/High-Density VLSI Circuits Woojin JIN Hanjong YOO Yungseon EO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/06/25 Vol. E82-C No. 6 ; pp. 955-966 Type of Manuscript: Special Section PAPER (Special Issue on TCAD for Semiconductor Industries) Category: Keyword: interconnect, substrate effect, shielding effect, signal integrity, signal delay, crosstalk noise,
	Summary \| Full Text:PDF