Keyword : settling time


A Logarithmic Compression ADC Using Transient Response of a Comparator
Yuji INAGAKI Yusaku SUGIMORI Eri IOKA Yasuyuki MATSUYA 
Publication:   
Publication Date: 2017/04/01
Vol. E100-C  No. 4 ; pp. 359-362
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
logarithmic compressionADCsubrangingTDClatched comparatorsettling time
 Summary | Full Text:PDF

Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers
Jun Gyu LEE Zule XU Shoichi MASUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/08/01
Vol. E95-A  No. 8 ; pp. 1337-1346
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
phase-locked loopfrequency synthesizerloop designsettling timeprocess variations
 Summary | Full Text:PDF