Keyword : sequential depth for testability


Non-scan Design for Testability for Synchronous Sequential Circuits Based on Fault-Oriented Conflict Analysis
Dong XIANG Shan GU Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/11/01
Vol. E86-D  No. 11 ; pp. 2407-2417
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
at-speed testconflictcontaining assignmentnon-scan design for testabilitysequential depth for testability
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