IEICE Trans

Keyword : sense amplifier

A Summer-Embedded Sense Amplifier for High-Speed Decision Feedback Equalizer Il-Min YI Naoki MIURA Hiroyuki FUKUYAMA Hideyuki NOSAKA
Publication: Publication Date: 2018/11/01 Vol. E101-A No. 11 ; pp. 1949-1951 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: sense amplifier, decision feedback equalizer, feedback loop delay, ISI, receiver,
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A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design Li-Rong WANG Kai-Yu LO Shyh-Jye JOU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/10/01 Vol. E96-C No. 10 ; pp. 1351-1355 Type of Manuscript: BRIEF PAPER Category: Electronic Circuits Keyword: double-edge-triggered, flip-flop, level-converting, sense amplifier, mixed threshold voltage,
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A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs Song JIA Heqing XU Fengfeng WU Yuan WANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/09/01 Vol. E96-C No. 9 ; pp. 1205-1207 Type of Manuscript: BRIEF PAPER Category: Integrated Electronics Keyword: SRAM, sense amplifier, winner-take-all, high speed,
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Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays Akira KOTABE Riichiro TAKEMURA Yoshimitsu YANAGAWA Tomonori SEKIGUCHI Kiyoo ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 ; pp. 594-599 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: DRAM, low voltage, sense amplifier, mid-point sensing,
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A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers Shinya KAJIYAMA Masamichi FUJITO Hideo KASAI Makoto MIZUNO Takanori YAMAGUCHI Yutaka SHINAGAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/10/01 Vol. E92-C No. 10 ; pp. 1258-1264 Type of Manuscript: Special Section PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors) Category: Keyword: flash memory, microcontroller, dual-core, shared ROM, pipeline, sense amplifier,
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Design of Asynchronous Multi-Bit OTP Memory Chul-Ho CHOI Jae-Hyung LEE Tae-Hoon KIM Oe-Yong SHIM Yoon-Geum HWANG Kwang-Seon AHN Pan-Bong HA Young-Hee KIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/01/01 Vol. E92-C No. 1 ; pp. 173-177 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: multi-bit OTP, two-transistor OTP cell, antifuse, sense amplifier,
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A High-Speed Current-Mode Multilevel Identifying Circuit for Flash Memories Hongchin LIN Funian LIANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/02/01 Vol. E86-C No. 2 ; pp. 229-235 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: current-mode, multilevel identifying circuit, flash memory, sense amplifier, offset,
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A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers Hiroaki YAMAOKA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/09/01 Vol. E84-C No. 9 ; pp. 1240-1246 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: high speed, PLA, array logic circuit, sense amplifier,
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Design and Analysis of Resonant-Tunneling-Diode (RTD) Based High Performance Memory System Tetsuya UEMURA Pinaki MAZUMDER
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-C No. 9 ; pp. 1630-1637 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Application of Resonant Tunneling Devices Keyword: resonant tunneling diode, DRAM, sense amplifier, instability, refresh-free,
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A 167-MHz 1-Mbit CMOS Synchronous Cache SRAM Hideharu YAHATA Yoji NISHIO Kunihiro KOMIYAJI Hiroshi TOYOSHIMA Atsushi HIRAISHI Yoshitaka KINOSHITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/04/25 Vol. E80-C No. 4 ; pp. 557-565 Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs) Category: Keyword: CMOS, high speed, cache SRAM, chip floor plan, sense amplifier, output register, setup/hold time,
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A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs Tsuneo INABA Daisaburo TAKASHIMA Yukihito OOWAKI Tohru OZAKI Shigeyoshi WATANABE Takashi OHSAWA Kazunori OHUCHI Hiroyuki TANGO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/25 Vol. E79-C No. 12 ; pp. 1699-1706 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: DRAM, power dissipation, reliability, bit-line, wordline, small swing, threshold voltage, sense amplifier, memory cell,
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High-Speed CMOS SRAM Technologies for Cache Applications Koichiro ISHIBASHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 ; pp. 724-734 Type of Manuscript: INVITED PAPER (Special Issue on ULSI Memory Technology) Category: Static RAMs Keyword: CMOS SRAM, cache, wave-pipelined, sense amplifier, low-voltage,
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A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories Hiroshi NAKAMURA Jun-ichi MIYAMOTO Ken-ichi IMAMIYA Yoshihisa IWATA Yoshihisa SUGIURA Hideko OODAIRA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/25 Vol. E79-C No. 6 ; pp. 836-844 Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology) Category: Nonvolatile memories Keyword: flash memory, sense amplifier, bit-by-bit program verify, capacitive coupling, page copy,
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