Keyword : scan design


Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents
Hideo FUJIWARA Katsuya FUJIWARA 
Publication:   
Publication Date: 2017/09/01
Vol. E100-D  No. 9 ; pp. 2232-2236
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designgeneralized feedback/feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(468.4KB)

Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design
Hideo FUJIWARA Katsuya FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/08/01
Vol. E99-D  No. 8 ; pp. 2182-2185
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designgeneralized feedback/feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(399.6KB)

Properties of Generalized Feedback Shift Registers for Secure Scan Design
Hideo FUJIWARA Katsuya FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/04/01
Vol. E99-D  No. 4 ; pp. 1255-1258
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designgeneralized feedback/feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(395.2KB)

Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers
Hideo FUJIWARA Katsuya FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/10/01
Vol. E98-D  No. 10 ; pp. 1852-1855
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designgeneralized feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(352.9KB)

Generalized Feed Forward Shift Registers and Their Application to Secure Scan Design
Katsuya FUJIWARA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/05/01
Vol. E96-D  No. 5 ; pp. 1125-1133
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designshift register equivalentsshift register quasi-equivalentsgeneralized feed-forward shift registerssecurityscan-based side-channel attack
 Summary | Full Text:PDF(1.7MB)

Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design
Katsuya FUJIWARA Hideo FUJIWARA Hideo TAMAMOTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/07/01
Vol. E94-D  No. 7 ; pp. 1430-1439
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
design-for-testabilityscan designshift register equivalentssecurityscan-based side-channel attack
 Summary | Full Text:PDF(599.1KB)

Design for Delay Fault Testability of 2-Rail Logic Circuits
Kentaroh KATOH Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/02/01
Vol. E92-D  No. 2 ; pp. 336-341
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
2-rail logic circuitsdesign for testabilitydelay fault testingscan designset-reset operation
 Summary | Full Text:PDF(455.8KB)

Scan Design for Two-Pattern Test without Extra Latches
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/12/01
Vol. E88-D  No. 12 ; pp. 2777-2785
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
two-pattern testingdelay fault testingscan designenhanced scan
 Summary | Full Text:PDF(1.5MB)

Embedded Memory Array Testing Using a Scannable Configuration
Seiken YANO Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1934-1944
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
scannable memory configurationmemory array testingdesign-for-testabilityscan design
 Summary | Full Text:PDF(823.2KB)

Compact Test Sequences for Scan-Based Sequential Circuits
Hiroyuki HIGUCHI Kiyoharu HAMAGUCHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1676-1683
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
test generationscan designtest application timeboolean function manipulation
 Summary | Full Text:PDF(688KB)