A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays Vasutan TUNBUNHENGHideharu AMANO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/11/01 Vol. E91-DNo. 11 ;
pp. 2655-2665 Type of Manuscript: PAPER Category: VLSI Systems Keyword: dynamically reconfigurable system, retargetable compiler,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-ANo. 12 ;
pp. 2595-2604 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Co-design Keyword: embedded system design, hardware/software codesign, retargetable compiler,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-ANo. 12 ;
pp. 2630-2639 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Compiler Keyword: retargetable compiler, binding, non-orthogonal architecture, DSP, binary decision diagram,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/09/25 Vol. E79-DNo. 9 ;
pp. 1248-1256 Type of Manuscript: PAPER Category: Sofware System Keyword: code generator, compiler, peephole optimizer, retargetable compiler,
