Keyword : refresh

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh
Hideyuki NODA Kazunari INOUE Hans Jurgen MATTAUSCH Tetsushi KOIDE Katsumi DOSAKA Kazutami ARIMOTO Kazuyasu FUJISHIMA Kenji ANAMI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 622-629
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Memory
Keyword: 
CMOS, Ternary CAM, network, refresh, 
 Summary | Full Text:PDF
Analyzing and Reducing the Impact of Shorter Data Retention Time on the Performance of Merged DRAM/Logic LSIs
Koji KAI Akihiko INOUE Taku OHSAWA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1448-1454
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
merged DRAM/logic LSIs, data retention time, refresh, yield, 
 Summary | Full Text:PDF
A Long Data Retention SOI DRAM with the Body Refresh Function
Shigeki TOMISHIMA Fukashi MORISHITA Masaki TSUKUDE Tadato YAMAGATA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7 ; pp. 899-904
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Novel Structure Devices
Keyword: 
memory, SOI-DRAM, body region, refresh, data retention, 
 Summary | Full Text:PDF
A Crossing Charge Recycle Refresh Scheme with a Separated Driver Sense-Amplifier for Gb DRAMs
Isao NARITAKE Tadahiko SUGIBAYASHI Satoshi UTSUGI Tatsunori MUROTANI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 787-791
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Dynamic RAMs
Keyword: 
memory, DRAM, hierarchical bit-line, refresh, 
 Summary | Full Text:PDF