Keyword : reconfiguration algorithm


A Graph-Theoretic Approach to Minimizing the Number of Dangerous Processors in Fault-Tolerant Mesh-Connected Processor Arrays
Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/11/01
Vol. E84-D  No. 11 ; pp. 1462-1470
Type of Manuscript:  Special Section PAPER (Special Issue on Function Integrated Information Systems)
Category: 
Keyword: 
fault tolerancereconfiguration algorithmdangerous processormesh-connected processor arraygraph-theoretic approach
 Summary | Full Text:PDF(626KB)

Reconfiguration Algorithm for Modular Redundant Linear Array
Chang CHEN An FENG Yoshiaki KAKUDA Tohru KIKUNO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/02/25
Vol. E76-D  No. 2 ; pp. 210-218
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
fault tolerant computingsystolic arrayN-modular redundancyreconfigurable modular redundant linear arrayreconfiguration algorithm
 Summary | Full Text:PDF(813KB)