IEICE Trans

Keyword : reconfigurable processor

Software Defined Modem for Cognitive Radio with Dynamically Reconfigurable Processor Ren SAKATA Daisuke TAKEDA Noritaka DEGUCHI Tatsuma HIRANO Takashi YOSHIKAWA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2012/03/01 Vol. E95-B No. 3 ; pp. 810-818 Type of Manuscript: PAPER Category: Transmission Systems and Transmission Equipment for Communications Keyword: software defined radio, reconfigurable processor, 3GPP long term evolution,
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A Reconfigurable Processor Infrastructure for Accelerating Java Applications Youngsun HAN Seok Joong HWANG Seon Wook KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/08/01 Vol. E91-A No. 8 ; pp. 2091-2100 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: reconfigurable processor, compiler framework, Java, VerilogHDL,
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Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs Farhad MEHDIPOUR Hamid NOORI Morteza SAHEB ZAMANI Koji INOUE Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/12/01 Vol. E90-D No. 12 ; pp. 1956-1966 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Reconfigurable Device and Design Tools Keyword: reconfigurable accelerator, conditional execution, control data flow graph, temporal partitioning, reconfigurable processor,
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Low-Power Field-Programmable VLSI Using Multiple Supply Voltages Weisheng CHONG Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 ; pp. 3298-3305 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Low Power Methodology Keyword: reconfigurable processor, FPGA, multiple-supply-voltage scheme,
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Design and Performance Evaluation of IEEE 802.11a SDR Software Implemented on a Reconfigurable Processor Kazunori AKABANE Hiroyuki SHIBA Munehiro MATSUI Kiyoshi KOBAYASHI Katsuhiko ARAKI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2005/11/01 Vol. E88-B No. 11 ; pp. 4163-4169 Type of Manuscript: Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications) Category: Keyword: software defined radio, reconfigurable processor, wireless LAN, IEEE 802.11a,
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Architecture of a Fine-Grain Field-Programmable VLSI Based on Multiple-Valued Source-Coupled Logic Md.Munirul HAQUE Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 ; pp. 1869-1875 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: reconfigurable processor, multiple-valued logic, bit-serial architecture, current mode logic,
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