Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-ANo. 7 ;
pp. 1345-1354 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: online task placement, reconfigurable device, efficient data structure, MER enumeration,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-DNo. 2 ;
pp. 324-334 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: reconfigurable device, physical design, placement, routing, MPLD, FPGA, EDA,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-ANo. 12 ;
pp. 3612-3621 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: fault tolerance, dependable, FPGA, reconfigurable device, soft error,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-CNo. 10 ;
pp. 1919-1926 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Low-Power and High-Performance VLSI Circuit Technology Keyword: variation-aware, reconfigurable device, FPGA, yield, DFM,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-CNo. 4 ;
pp. 699-707 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: within-die variation, reconfigurable device, FPGA, LUT (look-up table), yield,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/08/01 Vol. E87-DNo. 8 ;
pp. 2004-2010 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Recornfigurable Systems Keyword: FPGA, reconfigurable device, low-power, threshold voltage control, EDA,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2003/05/01 Vol. E86-DNo. 5 ;
pp. 850-858 Type of Manuscript: Special Section PAPER (Special Issue on Reconfigurable Computing) Category: Keyword: look-up table, static memory, reconfigurable device, transmission gate,
48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations