Keyword : reconfigurable device


An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device
Tieyuan PAN Li ZHU Lian ZENG Takahiro WATANABE Yasuhiro TAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1345-1354
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
online task placementreconfigurable deviceefficient data structureMER enumeration
 Summary | Full Text:PDF

A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks
Masatoshi NAKAMURA Masato INAGI Kazuya TANIGAWA Tetsuo HIRONAKA Masayuki SATO Takashi ISHIGURO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 324-334
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
reconfigurable devicephysical designplacementroutingMPLDFPGAEDA
 Summary | Full Text:PDF

Autonomous Repair Fault Tolerant Dynamic Reconfigurable Device
Kentaro NAKAHARA Shin'ichi KOUYAMA Tomonori IZUMI Hiroyuki OCHI Yukihiro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3612-3621
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
fault tolerancedependableFPGAreconfigurable devicesoft error
 Summary | Full Text:PDF

A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations
Kazutoshi KOBAYASHI Kazuya KATSUKI Manabu KOTANI Yuuri SUGIHARA Yohei KUME Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 1919-1926
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Low-Power and High-Performance VLSI Circuit Technology
Keyword: 
variation-awarereconfigurable deviceFPGAyieldDFM
 Summary | Full Text:PDF

A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations
Kazuya KATSUKI Manabu KOTANI Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 699-707
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
within-die variationreconfigurable deviceFPGALUT (look-up table)yield
 Summary | Full Text:PDF

Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity
Takashi KAWANAMI Masakazu HIOKI Hiroshi NAGASE Toshiyuki TSUTSUMI Tadashi NAKAGAWA Toshihiro SEKIGAWA Hanpei KOIKE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/08/01
Vol. E87-D  No. 8 ; pp. 2004-2010
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Recornfigurable Systems
Keyword: 
FPGAreconfigurable devicelow-powerthreshold voltage controlEDA
 Summary | Full Text:PDF

Evaluation and Comparison of Implementation Alternatives for Look-up Tables for Plastic Cell Architecture
Jun'ichiro TAKEMOTO Toshihiro GOTO Yuichiro SHIBATA Kiyoshi OGURI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5 ; pp. 850-858
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
look-up tablestatic memoryreconfigurable devicetransmission gate
 Summary | Full Text:PDF