Keyword : reconfigurable architecture


HyDRA: Hybrid Dynamically Reconfigurable Architecture for DSP Applications
Abdulfattah M. OBEID Syed Manzoor QASIM Mohammed S. BENSALEH Abdullah A. ALJUFFRI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/07/01
Vol. E99-C  No. 7 ; pp. 866-877
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
coarse-graineddigital signal processing (DSP)fine-grainedhybridreconfigurable architecture
 Summary | Full Text:PDF(3.1MB)

Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators
Yasuhiro TAKEI Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12 ; pp. 2658-2669
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
heterogeneous multicoreFPGAcustom acceleratorsreconfigurable architecture
 Summary | Full Text:PDF(2.3MB)

The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture
Rui SHI Shouyi YIN Leibo LIU Qiongbing LIU Shuang LIANG Shaojun WEI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2 ; pp. 276-287
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
reconfigurable architecturevideo up-scalingtextureparallelizationinterpolationsobel methodbilinearbicubic
 Summary | Full Text:PDF(1.9MB)

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing
Hiroaki KONOURA Dawood ALNAJJAR Yukio MITSUYAMA Hajime SHIMADA Kazutoshi KOBAYASHI Hiroyuki KANBARA Hiroyuki OCHI Takashi IMAGAWA Kazutoshi WAKABAYASHI Masanori HASHIMOTO Takao ONOYE Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2518-2529
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
reconfigurable architecturesoft errorradiation testbehavioral synthesisstate machine
 Summary | Full Text:PDF(3.8MB)

A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms
Shuangqu HUANG Xiaoyang ZENG Yun CHEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 403-412
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Application
Keyword: 
iterative decodingLDPC codesreconfigurable architectureTDMPTPMP
 Summary | Full Text:PDF(1.6MB)

Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband Platform
Shuang ZHAO Wenqing LU Xiaofang ZHOU Dian ZHOU Gerald E. SOBELMAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/04/01
Vol. E93-D  No. 4 ; pp. 811-821
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
MIMO-OFDMreconfigurable architectureFFTSTBDalgorithm implementation
 Summary | Full Text:PDF(1MB)

Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
Yiqing HUANG Qin LIU Satoshi GOTO Takeshi IKENAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/11/01
Vol. E92-A  No. 11 ; pp. 2819-2829
Type of Manuscript:  Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Video Coding
Keyword: 
reconfigurable architectureH.264/AVCSAD treeVLSIHDTV
 Summary | Full Text:PDF(1.3MB)

Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors
Ittetsu TANIGUCHI Praveen RAGHAVAN Murali JAYAPALA Francky CATTHOOR Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/04/01
Vol. E92-A  No. 4 ; pp. 1161-1173
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
address generation unit (AGU)reconfigurable architectureASIP designarchitecture exploration
 Summary | Full Text:PDF(1.1MB)

Temporal Partitioning to Amortize Reconfiguration Overhead for Dynamically Reconfigurable Architectures
Jinhwan KIM Jeonghun CHO Tag Gon KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12 ; pp. 1977-1985
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable Device and Design Tools
Keyword: 
temporal partitioningreconfigurable architecturepartial reconfigurationdynamic reconfigurationrun-time reconfiguration and high-level synthesis
 Summary | Full Text:PDF(688.2KB)

Reconfigurable Inner Product Hardware Architecture for Increased Hardware Utilization in SDR Systems
Kwangsup SO Jinsang KIM Won-Kyung CHO Young-Soo KIM Doug Young SUH 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2006/12/01
Vol. E89-B  No. 12 ; pp. 3242-3249
Type of Manuscript:  Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
inner productpipelined multiplierreconfigurable architecturesoftware defined radio
 Summary | Full Text:PDF(1014.2KB)

A Design Algorithm for Sequential Circuits Using LUT Rings
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3342-3350
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
reconfigurable architectureLUT cascadeBDD_for_CFfunctional decomposition
 Summary | Full Text:PDF(699.9KB)

Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture
Masanori HARIYAMA Weisheng CHONG Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1897-1902
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
reconfigurable architectureFPGAbit-serial architecture
 Summary | Full Text:PDF(530.8KB)

An Innovative Architecture of CMAC
Kao-Shing HWANG Yuan-Pao HSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/01/01
Vol. E87-C  No. 1 ; pp. 81-93
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
neural networkCMACCAMreconfigurable architecture
 Summary | Full Text:PDF(1.2MB)

An Efficiently Self-Reconstructing Array System Using E-1-Track Switches
Tadayoshi HORITA Itsuo TAKANAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/12/01
Vol. E86-D  No. 12 ; pp. 2743-2752
Type of Manuscript:  PAPER
Category: Fault Tolerance
Keyword: 
mesh-connected processor arrays1-track switchesE-1-track switchesfault-tolerancereconfigurable architecture
 Summary | Full Text:PDF(777.5KB)

A Low Cost Reconfigurable Architecture for a UMTS Receiver
Ronny VELJANOVSKI Aleksandar STOJCEVSKI Jugdutt SINGH Aladin ZAYEGH Michael FAULKNER 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/12/01
Vol. E86-B  No. 12 ; pp. 3441-3451
Type of Manuscript:  Special Section PAPER (Special Issue on Software Defined Radio Technology and Its Applications)
Category: 
Keyword: 
adjacent channel interferencepulse-shaping filterpipeline ADCreconfigurable architectureUTRA-TDD
 Summary | Full Text:PDF(891.5KB)

A Flexible Architecture for Digital Signal Processing
Wichai BOONKUMKLAO Yoshikazu MIYANAGA Kobchai DEJHAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/10/01
Vol. E86-D  No. 10 ; pp. 2179-2186
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
FRMPCAreconfigurable architectureIPVHDL
 Summary | Full Text:PDF(1.3MB)

PARS Architecture: A Reconfigurable Architecture with Generalized Execution Model--Design and Implementation of Its Prototype Processor
Kazuya TANIGAWA Tetsuo HIRONAKA Akira KOJIMA Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/05/01
Vol. E86-D  No. 5 ; pp. 830-840
Type of Manuscript:  Special Section PAPER (Special Issue on Reconfigurable Computing)
Category: 
Keyword: 
reconfigurable architectureI-PARS execution modelgeneral purposePARS architecturedesign and implementation
 Summary | Full Text:PDF(553.9KB)

RHINE: Reconfigurable Multiprocessor System for Video CODEC
Yoshinori TAKEUCHI Zhao-Chen HUANG Masatomo SAEKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6 ; pp. 947-956
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Methods and Circuits for Signal Processing
Keyword: 
parallel processingload balancingvideo CODECparallel architecturereconfigurable architecture
 Summary | Full Text:PDF(823.2KB)