Keyword : quasi-cyclic


A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS
Xiongxin ZHAO Zhixiang CHEN Xiao PENG Dajiang ZHOU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2623-2632
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
WiMAXbit-serialfully-parallellayered schedulingperformance awareadvanced dynamic quantizationquasi-cycliclow-density parity-check codes
 Summary | Full Text:PDF(2.2MB)

Design of Quasi-Cyclic Cycle LDPC Codes over GF(q)
ShuKai HU Chao CHEN Rong SUN XinMei WANG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2012/03/01
Vol. E95-B  No. 3 ; pp. 983-986
Type of Manuscript:  LETTER
Category: Fundamental Theories for Communications
Keyword: 
low-density parity-check (LDPC) codesnonbinaryquasi-cyclicminimum Hamming distancefast encoding
 Summary | Full Text:PDF(242KB)