IEICE Trans

Keyword : processor

Weight Compression MAC Accelerator for Effective Inference of Deep Learning Asuka MAKI Daisuke MIYASHITA Shinichi SASAKI Kengo NAKATA Fumihiko TACHIBANA Tomoya SUZUKI Jun DEGUCHI Ryuichi FUJIMOTO
Publication: Publication Date: 2020/10/01 Vol. E103-C No. 10 ; pp. 514-523 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Their Application Technologies) Category: Integrated Electronics Keyword: deep learning, convolutional neural network, quantization, variable bit width, post-training, inference, accelerator, processor, FPGA,
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Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor Yu SUZUKI Masato ITO Satoshi KANDA Kousuke IMAMURA Yoshio MATSUDA Tetsuya MATSUMURA
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 ; pp. 2888-2900 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: optical flow, HOE algorithm, SOR, FPGA, processor,
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Identification and Application of Invariant Critical Paths under NBTI Degradation Song BIAN Shumpei MORITA Michihiro SHINTANI Hiromitsu AWANO Masayuki HIROMOTO Takashi SATO
Publication: Publication Date: 2017/12/01 Vol. E100-A No. 12 ; pp. 2797-2806 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: NBTI, aging effect, invariant critical path, processor,
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Low Power Platform for Embedded Processor LSIs Toru SHIMIZU Kazutami ARIMOTO Osamu NISHII Sugako OTANI Hiroyuki KONDO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 ; pp. 394-400 Type of Manuscript: INVITED PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: low power, processor, operating system, distributed processing,
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Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors Masato NAKAZATO Michiko INOUE Satoshi OHTAKE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 ; pp. 763-770 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: High-Level Testing Keyword: software-based self-test, processor, test program template, design for testability, error masking, at-speed testing,
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High-End Server Based on Complexity-Reduced Architecture for Superconductor Technology Akira FUJIMAKI Yoshiaki TAKAI Nobuyuki YOSHIKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/03/01 Vol. E85-C No. 3 ; pp. 612-616 Type of Manuscript: INVITED PAPER (Special Issue on Superconductive Electronics) Category: Digital Devices and Their Applications Keyword: SFQ, memory, processor, superconducting circuit, JAVA,
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High-Speed Java^TM Runtime Environment for Embedded Equipment Shinji NAKAGAWA Yosuke BABA Yoshiaki MIYATA Hiroyuki YANAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 ; pp. 375-383 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Product Designs Keyword: Java, processor, KVM, CLDC, MIDP,
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Invariant-Free Formal Verification of Pipelined and Superscalar Controls by Behavior-Covering and Partial Unfolding Toru SHONAI Tsuguo SHIMIZU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/02/25 Vol. E82-D No. 2 ; pp. 376-388 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: formal verification, processor, pipeline, superscalar,
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Proposal for Incremental Formal Verification Toru SHONAI Kazuhiko MATSUMOTO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/11/25 Vol. E81-D No. 11 ; pp. 1172-1185 Type of Manuscript: PAPER Category: Computer Hardware and Design Keyword: formal verification, processor, pipeline, BDD, theorem prover,
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A New Processor Architecture for Digital Signal Transport Systems Minoru INAMORI Kenji ISHII Akihiro TSUTSUI Kazuhiro SHIRAKAWA Toshiaki MIYAZAKI Hiroshi NAKADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/25 Vol. E81-C No. 9 ; pp. 1408-1415 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: processor, VLSI, protocol processing, architecture,
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Formal Verification System for Pipelined Processors Toru SHONAI Tsuguo SHIMIZU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/06/25 Vol. E79-A No. 6 ; pp. 883-891 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: formal verification, pipeline, processor, correctness, mathematical induction,
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High-Level Synthesis of a Multithreaded Processor for Image Generation Takao ONOYE Toshihiro MASAKI Isao SHIRAKAWA Hiroaki HIRATA Kozo KIMURA Shigeo ASAHARA Takayuki SAGISHIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/03/25 Vol. E78-A No. 3 ; pp. 322-330 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems) Category: VLSI Design Technology and CAD Keyword: processor, multithread, parallel processing, high-level synthesis, image generation,
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A VLSI Processor Architecture for a Back-Propagation Accelerator Yoshio HIROSE Hideaki ANBUTSU Koichi YAMASHITA Gensuke GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/10/25 Vol. E75-C No. 10 ; pp. 1223-1231 Type of Manuscript: Special Section PAPER (Special Issue on Microprocessors) Category: Application Specific Processors Keyword: back-propagation, gate array, neural network, pipeline, processor,
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