Keyword : processor scheduling

Experimental Evaluation of Dynamic Scheduling for Parallel Logic Simulation Using Benchmark Circuits
Tadashi SEKO Tohru KIKUNO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11 ; pp. 1910-1912
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
parallel logic simulationprocessor scheduling
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