Keyword : processor architecture


An Inductive Method to Select Simulation Points
MinSeong CHOI Takashi FUKUDA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/12/01
Vol. E99-D  No. 12 ; pp. 2891-2900
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
simulation pointsampling simulationmicroarchitectureprocessor architecturesimulationcomputer architecture
 Summary | Full Text:PDF(2.6MB)

Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs
Shinya TAKAMAEDA-YAMAZAKI Hiroshi NAKATSUKA Yuichiro TANAKA Kenji KISE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/12/01
Vol. E98-D  No. 12 ; pp. 2150-2158
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
soft processorprocessor architectureFPGA
 Summary | Full Text:PDF(1MB)

Address Order Violation Detection with Parallel Counting Bloom Filters
Naruki KURATA Ryota SHIOYA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7 ; pp. 580-593
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
processor architectureload-store queuebloom filterlow-energy technologies
 Summary | Full Text:PDF(1.8MB)

Register Indirect Jump Target Forwarding
Ryota SHIOYA Naruki KURATA Takashi TOYOSHIMA Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/02/01
Vol. E96-D  No. 2 ; pp. 278-288
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architectureregister indirect jumpobject-oriented programming
 Summary | Full Text:PDF(1.7MB)

Architecture and Implementation of a Reduced EPIC Processor
Jun GAO Minxuan ZHANG Zuocheng XING Chaochao FENG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/01/01
Vol. E96-D  No. 1 ; pp. 9-18
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
ILPEPICIA-64processor architecturehardware implementation
 Summary | Full Text:PDF(1.8MB)

Low-Overhead Architecture for Security Tag
Ryota SHIOYA Daewung KIM Kazuo HORIO Masahiro GOSHIMA Shuichi SAKAI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/01/01
Vol. E94-D  No. 1 ; pp. 69-78
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
processor architecturetagged architectureinformation securityinformation flow tracking
 Summary | Full Text:PDF(507.1KB)

VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation
Noriyuki MINEGISHI Junichi MIYAKOSHI Yuki KURODA Tadayoshi KATAGIRI Yuki FUKUYAMA Ryo YAMAMOTO Masayuki MIYAMA Kousuke IMAMURA Hideo HASHIMOTO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 230-242
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: System LSIs and Microprocessors
Keyword: 
optical flowprocessor architecturevideo segmentation
 Summary | Full Text:PDF(4.2MB)

Reducing Memory System Energy by Software-Controlled On-Chip Memory
Masaaki KONDO Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 580-588
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword: 
processor architecturecacheon-chip memoryway activationmemory traffic
 Summary | Full Text:PDF(886.6KB)

Code Efficiency Evaluation for Embedded Processors
Morgan Hirosuke MIKI Mamoru SAKAMOTO Shingo MIYAMOTO Yoshinori TAKEUCHI Toyohiko YOSHIDA Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4 ; pp. 811-818
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
code efficiencyprofilingprocessor architecture
 Summary | Full Text:PDF(902.8KB)

Reducing Cache Energy Dissipation by Using Dual Voltage Supply
Vasily G. MOSHNYAGA Hiroshi TSUJI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2762-2768
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
cacheprocessor architecturelow-power
 Summary | Full Text:PDF(478.8KB)

Trends in High-Performance, Low-Power Processor Architectures
Kazuaki MURAKAMI Hidetaka MAGOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2 ; pp. 131-138
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
processor architecturehigh performance designlow power design
 Summary | Full Text:PDF(185.1KB)

ASIC Approaches for Vision-Based Vehicle Guidance
Ichiro MASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/25
Vol. E76-C  No. 12 ; pp. 1735-1743
Type of Manuscript:  INVITED PAPER (Special Issue on ASICs for Automotive Electronics)
Category: 
Keyword: 
ASICstereo visionintelligent vehiclesprocessor architecture
 Summary | Full Text:PDF(924.8KB)