Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/08/01 Vol. E95-ANo. 8 ;
pp. 1337-1346 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: phase-locked loop, frequency synthesizer, loop design, settling time, process variations,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-ANo. 12 ;
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Statistical Skew Modeling and Clock Period Optimization of Wafer Scale H-Tree Clock Distribution Network Xiaohong JIANGSusumu HORIGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/11/01 Vol. E84-DNo. 11 ;
pp. 1476-1485 Type of Manuscript: Special Section PAPER (Special Issue on Function Integrated Information Systems) Category: Keyword: H-tree, clock skew, clock delay, clock period, process variations,
