IEICE Trans

Keyword : process variation

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization Yu HU Jing YE Zhiping SHI Xiaowei LI
Publication: Publication Date: 2017/02/01 Vol. E100-D No. 2 ; pp. 323-331 Type of Manuscript: PAPER Category: Dependable Computing Keyword: process variation, timing variation, sample, path selection, least square,
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A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model Ahmed AWAD Atsushi TAKAHASHI Chikaaki KODAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-A No. 12 ; pp. 2363-2374 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: pattern fidelity, process variation, mask manufacturability, mask data volume, computation time,
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A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/07/01 Vol. E99-A No. 7 ; pp. 1278-1293 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: high-level synthesis, process variation, interconnection delay, distributed-register architecture, scenario,
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Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs Michitarou YABUUCHI Ryo KISHIDA Kazutoshi KOBAYASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 ; pp. 2367-2372 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: BTI, process variation, reliability,
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Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis Shiho HAGIWARA Takanori DATE Kazuya MASU Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/04/01 Vol. E97-C No. 4 ; pp. 280-288 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology) Category: Keyword: design for manufacturing, Monte Carlo method, importance sampling, SRAM, process variation, yield, norm minimization, Gaussian mixture models, clustering, hypersphere sampling,
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A Method for Minimizing Clock Skew Fluctuations Caused by Interconnect Process Variations Susumu KOBAYASHI Fumihiro MINAMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/09/01 Vol. E96-D No. 9 ; pp. 1980-1985 Type of Manuscript: Special Section PAPER (Special Section on Dependable Computing) Category: Keyword: clock skew, interconnect, process variation, signal delay,
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A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning Shuta KIMURA Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 ; pp. 2292-2300 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: post-silicon tuning, body bias clustering, process variation, body biasing, statistical static timing analysis,
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A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits Junya KAWASHIMA Hiroshi TSUTSUI Hiroyuki OCHI Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 ; pp. 2242-2250 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: subthreshold operation, process variation, minimum operation voltage estimation, energy minimization, yield maximization,
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Layout-Aware Variability Characterization of CMOS Current Sources Bo LIU Bo YANG Shigetoshi NAKATAKE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 ; pp. 696-705 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: process variation, current mismatch, layout-dependent variation, analog DFM,
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A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing Yohei NAKATA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 ; pp. 523-533 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: network-on-chip, process variation, adaptive circuits, routing algorithm,
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Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit Kei MATSUMOTO Tetsuya HIROSE Yuji OSAKI Nobutaka KUROKI Masahiro NUMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 ; pp. 1042-1048 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: SRAM, threshold voltage variation, compensation circuit, process variation, temperature variation, PVT variation,
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Stochastic Non-homogeneous Arnoldi Method for Analysis of On-Chip Power Grid Networks under Process Variations Zhihua GUI Fan YANG Xuan ZENG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 ; pp. 504-510 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: process variation, power grid, non-homogeneous, ARnoldi,
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Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits Pei-Wen LUO Jwu-E CHEN Chin-Long WEY
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-A No. 1 ; pp. 352-361 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: yield enhancement, mismatch, common centroid, spatial correlation, process variation, placement optimization,
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Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield Maximization Mahmoud MOMTAZPOUR Maziar GOUDARZI Esmaeil SANAEI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 ; pp. 2542-2550 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: process variation, task scheduling, power yield, MPSoC,
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A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation Takumi UEZONO Kazuya MASU Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 ; pp. 324-331 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: voltage measurement, spatial voltage drop fluctuation, process variation, power/signal integrity,
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Testable Critical Path Selection Considering Process Variation Xiang FU Huawei LI Xiaowei LI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/01/01 Vol. E93-D No. 1 ; pp. 59-67 Type of Manuscript: PAPER Category: Dependable Computing Keyword: testable critical path selection, process variation,
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Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 ; pp. 3079-3081 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: voltage-controlled oscillator, process variation, process compensation, body bias, current reference,
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Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations Takaaki OKUMURA Atsushi KUROKAWA Hiroo MASUDA Toshiki KANAMOTO Masanori HASHIMOTO Hiroshi TAKAFUJI Hidenari NAKASHIMA Nobuto ONO Tsuyoshi SAKATA Takashi SATO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 ; pp. 990-997 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: SSTA, output, transition time, gate delay model, process variation,
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One-Shot Voltage-Measurement Circuit Utilizing Process Variation Takumi UEZONO Takashi SATO Kazuya MASU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 ; pp. 1024-1030 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies Emerging Mainly from the 21st Workshop on Circuits and Systems in Karuizawa) Category: Keyword: voltage measurement, process variation, power/signal integrity,
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A Linear Fractional Transform (LFT) Based Model for Interconnect Uncertainty Omar HAFIZ Alexander MITEV Janet Meiling WANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/04/01 Vol. E92-A No. 4 ; pp. 1148-1160 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: uncertainty, process variation, variational model order reduction, linear fractional transform (LFT), balanced truncation realization (BTR), linear matrix inequality (LMI),
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A Power Grid Optimization Algorithm by Observing Timing Error Risk by IR Drop Yoshiyuki KAWAKAMI Makoto TERAO Masahiro FUKUI Shuji TSUKIYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 ; pp. 3423-3430 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power grid optimization, timing violation, critical path, process variation, IR drop,
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Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays Atsushi KUROKAWA Hiroo MASUDA Junko FUJII Toshinori INOSHITA Akira KASEBE Zhangcai HUANG Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 ; pp. 856-864 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: interconnect, worst-case delay, static timing analysis, process variation, capacitance extraction,
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Interconnect Modeling in Deep-Submicron Design Won-Young JUNG Soo-Young OH Jeong-Taek KONG Keun-Ho LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/08/25 Vol. E83-C No. 8 ; pp. 1311-1316 Type of Manuscript: INVITED PAPER (Special Issue on 1999 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'99)) Category: Circuit Applications Keyword: statistical interconnect library generation, interconnect modeling, Monte Carlo method, process variation,
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