IEICE Trans

Keyword : power gating

Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme Daisuke SUZUKI Takahiro HANYU
Publication: Publication Date: 2017/08/01 Vol. E100-D No. 8 ; pp. 1618-1624 Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing) Category: VLSI Architecture Keyword: field-programmable gate array (FPGA), power gating, magnetic tunnel junction (MTJ) device, and low power digital,
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An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications Atsushi KOSHIBA Mikiko SATO Kimiyoshi USAMI Hideharu AMANO Ryuichi SAKAMOTO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/08/01 Vol. E99-C No. 8 ; pp. 926-935 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: energy conservation, power gating, operating system, microprocessor,
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Reducing Aging Effects on Ternary CAM Ing-Chao LIN Yen-Han LEE Sheng-Wei WANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2016/07/01 Vol. E99-C No. 7 ; pp. 878-891 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: ternary content addressable memory (CAM), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), reliability, power gating,
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A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units Atsushi KOSHIBA Motoki WADA Ryuichi SAKAMOTO Mikiko SATO Tsubasa KOSAKA Kimiyoshi USAMI Hideharu AMANO Masaaki KONDO Hiroshi NAKAMURA Mitaro NAMIKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/07/01 Vol. E98-C No. 7 ; pp. 559-568 Type of Manuscript: Special Section PAPER (Special Section on Low-Power and High-Speed Chips) Category: Keyword: energy conservation, power gating, operating system, Linux,
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Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure Yasumichi TAKAI Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 ; pp. 2220-2225 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Design Keyword: power gating, on-chip power supply noise, rush current, well structure,
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A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm CMOS for Wireless Sensor Network Lechang LIU Takayasu SAKURAI Makoto TAKAMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/06/01 Vol. E95-C No. 6 ; pp. 1035-1041 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: injection lock, power gating, low noise amplifier, ultra low power,
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On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction Jinmyoung KIM Toru NAKURA Hidehiro TAKATA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 ; pp. 643-650 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: resonant supply noise, switched parasitic capacitors, sleep block, power gating,
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Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling Benjamin DEVLIN Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 ; pp. 546-554 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: power gating, gate-level, pipeline, self synchronous, energy minimum operation, FPGA,
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Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model Seidai TAKEDA Kyundong KIM Hiroshi NAKAMURA Kimiyoshi USAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 ; pp. 2499-2509 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: power gating, MTCMOS, delay, leakage power,
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On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch Jinmyoung KIM Toru NAKURA Hidehiro TAKATA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 ; pp. 511-519 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: power supply noise, resonance, parasitic capacitance, sleep block, DVS, power gating,
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Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity Lei CHEN Shinji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 ; pp. 3111-3118 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: power gating, multi-threshold CMOS (MTCMOS), controlling value, dynamic power reduction, maximum depth constraint, CV-based power gating,
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An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise Yasumi NAKAMURA Makoto TAKAMIYA Takayasu SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 ; pp. 468-474 Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era) Category: Keyword: power integrity, power gating, wake-up, dynamic voltage and frequency scaling, noise canceller,
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Fine-Grained Power Gating Based on the Controlling Value of Logic Elements Lei CHEN Takashi HORIYAMA Yuichi NAKAMURA Shinji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 ; pp. 3531-3538 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: power gating, multi-threshold CMOS (MTCMOS) technology, BDD, controlling value, leakage power reduction,
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