Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-ANo. 12 ;
pp. 3251-3257 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Design Keyword: crosstalk noise, capacitive coupling noise, transistor sizing, gate sizing, post-layout optimization,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-ANo. 11 ;
pp. 2769-2777 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Optimization of Power and Timing Keyword: transistor sizing, low power design, cell-base design, post-layout optimization, gate sizing,
