Keyword : post-layout optimization


Crosstalk Noise Optimization by Post-Layout Transistor Sizing
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3251-3257
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
crosstalk noisecapacitive coupling noisetransistor sizinggate sizingpost-layout optimization
 Summary | Full Text:PDF

Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2769-2777
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
transistor sizinglow power designcell-base designpost-layout optimizationgate sizing
 Summary | Full Text:PDF