IEICE Trans

Keyword : placement

Flow Clustering Based Efficient Consolidated Middlebox Positioning Approach for SDN/NFV-Enabled Network Duc Tiep VU Kyungbaek KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2016/08/01 Vol. E99-D No. 8 ; pp. 2177-2181 Type of Manuscript: LETTER Category: Information Network Keyword: consolidated middlebox, flow clustering, placement, SDN, NFV, service chain,
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A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization Yiqiang SHENG Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/12/01 Vol. E97-A No. 12 ; pp. 2418-2426 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: NP-hard problem, optimization, conflicting objectives, physical design, placement,
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A Method of Analog IC Placement with Common Centroid Constraints Keitaro UE Kunihiro FUJIYOSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/01/01 Vol. E97-A No. 1 ; pp. 339-346 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: analog circuits, placement, symmetry constraints, sequence-pair,
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Sparse Placement of Wavelength Convertible 3R Regenerators and Joint Resource Assignment in Large-Scale Optical Networks Xin WANG Filippos BALASIS Sugang XU Yoshiaki TANAKA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2013/07/01 Vol. E96-B No. 7 ; pp. 1845-1856 Type of Manuscript: PAPER Category: Network Keyword: wavelength, conversion, 3R regeneration, placement, routing, assignment, cost, benefit, optical, network,
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Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips Wei ZHONG Takeshi YOSHIMURA Bei YU Song CHEN Sheqin DONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 ; pp. 534-545 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: networks on chip (NoC), placement, synthesis, topology,
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A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks Masatoshi NAKAMURA Masato INAGI Kazuya TANIGAWA Tetsuo HIRONAKA Masayuki SATO Takashi ISHIGURO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 ; pp. 324-334 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: reconfigurable device, physical design, placement, routing, MPLD, FPGA, EDA,
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Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming Qing DONG Bo YANG Jing LI Shigetoshi NAKATAKE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 ; pp. 3103-3110 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verfication Keyword: placement, floorplan, buffer insertion, module resizing, geometric programming,
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Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage Liangpeng GUO Yici CAI Qiang ZHOU Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/08/01 Vol. E91-A No. 8 ; pp. 2084-2090 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: voltage island, level converter, low power, placement,
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Voltage Island Generation in Cell Based Dual-Vdd Design Yici CAI Bin LIU Qiang ZHOU Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/01/01 Vol. E90-A No. 1 ; pp. 267-273 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: dual-Vdd, layout, placement, voltage island, voltage assignment,
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Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model Hidenari NAKASHIMA Junpei INOUE Kenichi OKADA Kazuya MASU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 ; pp. 3358-3366 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: interconnect, layout compaction, physical design, placement, core utilization,
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EQ-Sequences for Coding Floorplans Hua-An ZHAO Chen LIU Yoji KAJITANI Keishi SAKANUSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 ; pp. 3233-3243 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Floorplan Keyword: floorplan, placement, VLSI CAD, Q-sequence,
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VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing Sheqin DONG Xianlong HONG Song CHEN Xin QI Ruijie WANG Jun GU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 3136-3147 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Place and Routing Keyword: floorplan, placement, solution space smoothing,
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A Hybrid Force-Directed Self-Organizing Neural Network Approach to Automatic Printed Circuit Board Component Placement with EMC Consideration Teck Lin ANG Yuji TARUI Takashi SAKUSABE Takehiro TAKAHASHI Noboru SCHIBUYA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2002/09/01 Vol. E85-B No. 9 ; pp. 1797-1805 Type of Manuscript: PAPER Category: Electromagnetic Compatibility(EMC) Keyword: EMC, PCB, force-directed method, placement, neural network,
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The 3D-Packing by Meta Data Structure and Packing Heuristics Hiroyuki YAMAZAKI Keishi SAKANUSHI Shigetoshi NAKATAKE Yoji KAJITANI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/04/25 Vol. E83-A No. 4 ; pp. 639-645 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: 3D-packing, placement, sequence-pair, sequence-triple, simulated annealing,
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Rectilinear Shape Formation Method on Block Placement Kazuhisa OKADA Takayuki YAMANOUCHI Takashi KAMBE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/03/25 Vol. E81-A No. 3 ; pp. 446-454 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems) Category: Keyword: floorplan, rectilinear, soft block, placement,
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A New Approach of Fractal-Analysis Based Module Clustering for VLSI Placement Masahiko TOYONAGA Shih-Tsung YANG Isao SHIRAKAWA Toshiro AKINO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/25 Vol. E77-A No. 12 ; pp. 2045-2052 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: clustering, fractal analysis, placement, partitioning,
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Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/12/25 Vol. E77-A No. 12 ; pp. 2028-2038 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: FPGA, look up table, technology mapping, layout design, placement, global routing,
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Wire Length Expressions for Analytical Placement Approach Shoichiro YAMADA Masahiro KASAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/04/25 Vol. E77-A No. 4 ; pp. 716-718 Type of Manuscript: LETTER Category: Computer Aided Design (CAD) Keyword: placement, CAD, VLSI design,
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Timing Driven Placement Based on Fuzzy Theory Ze Cang GU Shoichiro YAMADA Shojiro YONEDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/07/25 Vol. E75-A No. 7 ; pp. 917-919 Type of Manuscript: Special Section LETTER (Special Section on the 1992 IEICE Spring Conference) Category: Keyword: fuzzy, timing, placement, VLSI,
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A Layout System for Mixed A/D Standard Cell LSI's Ikuo HARADA Hitoshi KITAZAWA Takao KANEKO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/03/25 Vol. E75-C No. 3 ; pp. 322-332 Type of Manuscript: Special Section PAPER (Special Issue on Analog LSI and Related Technology) Category: Keyword: analog layout, floorplan, placement, global routing, channel routing, crossovers, crosstalk noise,
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Cell Designer: An Automatic Placement and Routing Tool for the Mixed Design of Macro and Standard Cells Young Seok BAEK Byoung Yoon CHEON Kyung Sik KIM Hyun Chan LEE Chul Dong LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1992/02/25 Vol. E75-A No. 2 ; pp. 224-232 Type of Manuscript: PAPER Category: Computer Aided Design (CAD) Keyword: VLSI/CAD, layout, placement, routing, macro cell, standard cell,
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