Keyword : pipelining


High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA
Piyumal RANAWAKA Mongkol EKPANYAPONG Adriano TAVARES Mathew DAILEY Krit ATHIKULWONGSE Vitor SILVA 
Publication:   
Publication Date: 2019/12/01
Vol. E102-A  No. 12 ; pp. 1792-1803
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
application specific architecturehardware accelerationpipeliningreal-time HOG-SVM
 Summary | Full Text:PDF(3.1MB)

High-Performance End-to-End Integrity Verification on Big Data Transfer
Eun-Sung JUNG Si LIU Rajkumar KETTIMUTHU Sungwook CHUNG 
Publication:   
Publication Date: 2019/08/01
Vol. E102-D  No. 8 ; pp. 1478-1488
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
high-performance data transferIoT-based big datadata integritypipelining
 Summary | Full Text:PDF(870.1KB)

Tuning GridFTP Pipelining, Concurrency and Parallelism Based on Historical Data
Jangyoung KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/11/01
Vol. E97-D  No. 11 ; pp. 2963-2966
Type of Manuscript:  LETTER
Category: Information Network
Keyword: 
big datathroughput optimizationthroughput estimationpipeliningconcurrencyparallelism
 Summary | Full Text:PDF(342KB)

A Pipelined Architecture for Intra PU Encoding in HEVC
Yunpyo HONG Juwon BYUN Youngjo KIM Jaeseok KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/06/01
Vol. E97-A  No. 6 ; pp. 1439-1442
Type of Manuscript:  LETTER
Category: Image
Keyword: 
HEVCIntra predictionrough mode decision (RMD)rate distortion optimization (RDO)pipelining
 Summary | Full Text:PDF(689.2KB)

A Processor Accelerator for Software Decoding of BCH Codes
Kazuhito ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7 ; pp. 1329-1337
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
error correction codeBCHacceleratorpipelining
 Summary | Full Text:PDF(841.7KB)

Design and Efficient Implementation of a Modulated Complex Lapped Transform Processor Using Pipelining Technique
Heng-Ming TAI Changyou JING 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/05/01
Vol. E84-A  No. 5 ; pp. 1280-1287
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
modulated lapped transformFFTDCTpipeliningprogrammable logic device
 Summary | Full Text:PDF(594.2KB)

Unified Fully-Pipelined VLSI Implementations of the One- and Two-Dimensional Real Discrete Trigonometric Transforms
Wen-Hsien FANG Ming-Lu WU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/10/25
Vol. E82-A  No. 10 ; pp. 2219-2230
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
discrete trigonometric transformsVLSI array processorsClenshaw's recurrencepipeliningdigital signal processing
 Summary | Full Text:PDF(747.8KB)

Pipelined Architecture of the LMS Adaptive Digital Filter with the Minimum Output Latency
Akio HARADA Kiyoshi NISHIKAWA Hitoshi KIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/08/25
Vol. E81-A  No. 8 ; pp. 1578-1585
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
pipeliningLMS algorithmoutput latencyadaptive digital filter
 Summary | Full Text:PDF(566.9KB)

2-D Pipelined Adaptive Filters Based on 2-D Delayed LMS Algorithm
Katsushige MATSUBARA Kiyoshi NISHIKAWA Hitoshi KIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Vol. E80-A  No. 6 ; pp. 1009-1014
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
Category: 
Keyword: 
pipeliningtwo-dimensional LMS algorithmdelayed LMS algorithm
 Summary | Full Text:PDF(416.8KB)

A 50 MHz CMOS Pipelined Majority Logic Decoder for (1057, 813) Difference-Set Cyclic Code
Kazumasa KOBAYASHI Kouji YAMANO Hideki KOKUBUN Kiichi KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/07/25
Vol. E79-A  No. 7 ; pp. 1060-1067
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
difference-set cyclic codes(1057,813) codemajority logic decodingpipelining
 Summary | Full Text:PDF(623.9KB)

Pipelining Gauss Seidel Method for Analysis of Discrete Time Cellular Neural Networks
Naohiko SHIMIZU Gui-Xin CHENG Munemitsu IKEGAMI Yoshinori NAKAMURA Mamoru TANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/08/25
Vol. E77-A  No. 8 ; pp. 1396-1403
Type of Manuscript:  PAPER
Category: Neural Networks
Keyword: 
cellular neural networksdynamicsnumerical analysisrelaxation methodpipeliningimage codingimage decodingstructural compressionregularizationcommunication system
 Summary | Full Text:PDF(693.2KB)