IEICE Trans

Keyword : pipelining

High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA Piyumal RANAWAKA Mongkol EKPANYAPONG Adriano TAVARES Mathew DAILEY Krit ATHIKULWONGSE Vitor SILVA
Publication: Publication Date: 2019/12/01 Vol. E102-A No. 12 ; pp. 1792-1803 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: application specific architecture, hardware acceleration, pipelining, real-time HOG-SVM,
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High-Performance End-to-End Integrity Verification on Big Data Transfer Eun-Sung JUNG Si LIU Rajkumar KETTIMUTHU Sungwook CHUNG
Publication: Publication Date: 2019/08/01 Vol. E102-D No. 8 ; pp. 1478-1488 Type of Manuscript: PAPER Category: Fundamentals of Information Systems Keyword: high-performance data transfer, IoT-based big data, data integrity, pipelining,
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Tuning GridFTP Pipelining, Concurrency and Parallelism Based on Historical Data Jangyoung KIM
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2014/11/01 Vol. E97-D No. 11 ; pp. 2963-2966 Type of Manuscript: LETTER Category: Information Network Keyword: big data, throughput optimization, throughput estimation, pipelining, concurrency, parallelism,
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A Pipelined Architecture for Intra PU Encoding in HEVC Yunpyo HONG Juwon BYUN Youngjo KIM Jaeseok KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2014/06/01 Vol. E97-A No. 6 ; pp. 1439-1442 Type of Manuscript: LETTER Category: Image Keyword: HEVC, Intra prediction, rough mode decision (RMD), rate distortion optimization (RDO), pipelining,
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A Processor Accelerator for Software Decoding of BCH Codes Kazuhito ITO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/07/01 Vol. E93-A No. 7 ; pp. 1329-1337 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: error correction code, BCH, accelerator, pipelining,
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Design and Efficient Implementation of a Modulated Complex Lapped Transform Processor Using Pipelining Technique Heng-Ming TAI Changyou JING
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/05/01 Vol. E84-A No. 5 ; pp. 1280-1287 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: modulated lapped transform, FFT, DCT, pipelining, programmable logic device,
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Unified Fully-Pipelined VLSI Implementations of the One- and Two-Dimensional Real Discrete Trigonometric Transforms Wen-Hsien FANG Ming-Lu WU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/10/25 Vol. E82-A No. 10 ; pp. 2219-2230 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: discrete trigonometric transforms, VLSI array processors, Clenshaw's recurrence, pipelining, digital signal processing,
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Pipelined Architecture of the LMS Adaptive Digital Filter with the Minimum Output Latency Akio HARADA Kiyoshi NISHIKAWA Hitoshi KIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/08/25 Vol. E81-A No. 8 ; pp. 1578-1585 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Keyword: pipelining, LMS algorithm, output latency, adaptive digital filter,
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2-D Pipelined Adaptive Filters Based on 2-D Delayed LMS Algorithm Katsushige MATSUBARA Kiyoshi NISHIKAWA Hitoshi KIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/06/25 Vol. E80-A No. 6 ; pp. 1009-1014 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96)) Category: Keyword: pipelining, two-dimensional LMS algorithm, delayed LMS algorithm,
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A 50 MHz CMOS Pipelined Majority Logic Decoder for (1057, 813) Difference-Set Cyclic Code Kazumasa KOBAYASHI Kouji YAMANO Hideki KOKUBUN Kiichi KOBAYASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/07/25 Vol. E79-A No. 7 ; pp. 1060-1067 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: difference-set cyclic codes, (1057,813) code, majority logic decoding, pipelining,
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Pipelining Gauss Seidel Method for Analysis of Discrete Time Cellular Neural Networks Naohiko SHIMIZU Gui-Xin CHENG Munemitsu IKEGAMI Yoshinori NAKAMURA Mamoru TANAKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/08/25 Vol. E77-A No. 8 ; pp. 1396-1403 Type of Manuscript: PAPER Category: Neural Networks Keyword: cellular neural networks, dynamics, numerical analysis, relaxation method, pipelining, image coding, image decoding, structural compression, regularization, communication system,
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