Keyword : pipelined architecture


Design and Evaluation of a High Speed Routing Lookup Architecture
Jun ZHANG JeoungChill SHIM Hiroyuki KURINO Mitsumasa KOYANAGI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2004/03/01
Vol. E87-B  No. 3 ; pp. 406-412
Type of Manuscript:  Special Section PAPER (Special Section on Internet Technology IV)
Category: Implementation and Operation
Keyword: 
IP routingselective binary search algorithmpipelined architecturecache
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A High Throughput Pipelined Architecture for Blind Adaptive Equalizer with Minimum Latency
Masashi MIZUNO James OKELLO Hiroshi OCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/08/01
Vol. E86-A  No. 8 ; pp. 2011-2019
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
blind equalizerCMAcritical pathpipelined architecture
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Address Addition and Decoding without Carry Propagation
Yung-Hei LEE Seung Ho HWANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1 ; pp. 98-100
Type of Manuscript:  LETTER
Category: Algorithm and Computational Complexity
Keyword: 
decodingcache memorymemory latencypipelined architectureparallel adderscarry propagation
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An Instruction Set Optimization Algorithm for Pipelined ASIPs
Nguyen Ngoc BINH Masaharu IMAI Akichika SHIOMI Nobuyuki HIKICHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1707-1714
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
ASIPpipelined architectureHW/SW partitioningperformance estimationPEAS-I system
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