A Pipeline Chip for Quasi Arithmetic Coding Yair WISEMAN
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/04/01 Vol. E84-ANo. 4 ;
pp. 1034-1041 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: pipeline structure, compression, arithmetic coding, hardware-software combination,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/06/25 Vol. E82-ANo. 6 ;
pp. 920-926 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98)) Category: Keyword: sequential Boltzmann machine, neural network, pipeline structure, parallel-transit-evaluation algorithm,