Keyword : pin assignment

A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout
Tetsushi KOIDE Shin'ichi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2476-2484
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Optimization
Keyword: 
building block layout, global routing, pin assignment, timing constraint, simulated evolution, 
 Summary | Full Text:PDF(880.2KB)
A Pin Assignment and Global Routing Algorithm for Floorplanning
Takahiro SHIOHARA Masahiro FUKUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/08/25
Vol. E81-A  No. 8 ; pp. 1725-1732
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
floorplan, pin assignment, global route, maximum flow algorithm, 
 Summary | Full Text:PDF(850.2KB)
Effect of Power and Ground Pin Assignment and Inner Layer Structure on Switching Noise
Nobuaki SUGIURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/05/25
Vol. E78-C  No. 5 ; pp. 574-579
Type of Manuscript:  PAPER
Category: Components
Keyword: 
switching noise, pin assignment, connector, 
 Summary | Full Text:PDF(410.5KB)