Keyword : phase-locked loop (PLL)


1.5-GHz Spread-Spectrum PHY Using Reference Clock with 400-ppm Frequency Tolerance for SATA Application
Takashi KAWAMOTO Masato SUZUKI Takayuki NOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/02/01
Vol. E98-A  No. 2 ; pp. 485-491
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
calibrationserial ATAphase-locked loop (PLL)spread-spectrum clock generator (SSCG)
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A Monolithic Sub-sampling PLL based 6–18 GHz Frequency Synthesizer for C, X, Ku Band Communication
Hanchao ZHOU Ning ZHU Wei LI Zibo ZHOU Ning LI Junyan REN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/01/01
Vol. E98-C  No. 1 ; pp. 16-27
Type of Manuscript:  PAPER
Category: Microwaves, Millimeter-Waves
Keyword: 
sub-samplingfrequency synthesizerphase-locked loop (PLL)SSB mixerinjection-locked frequency doublerradar system
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The Design of a K-Band 0.8-V 9.2-mW Phase-Locked Loop
Zue-Der HUANG Chung-Yu WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/08/01
Vol. E94-C  No. 8 ; pp. 1289-1294
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
phase-locked loop (PLL)VCOcoupling current-mode injection-locked frequency divider (CCMILFD)SPR-PFDcomplementary-type charge pump
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A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application
Kuo-Hsing CHENG Yu-Chang TSAI Chien-Nan Jimmy LIU Kai-Wei HONG Chin-Cheng KUO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/07/01
Vol. E92-C  No. 7 ; pp. 964-972
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
phase-locked loop (PLL)self-calibrationlow jittermulti-phase VCO
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A New Charge Pump PLL with Reduced Jitter
Yu-Gun KIM Myoung-Su LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2001/06/01
Vol. E84-B  No. 6 ; pp. 1680-1682
Type of Manuscript:  LETTER
Category: Communication Devices/Circuits
Keyword: 
charge pumpphase-locked loop (PLL)jitter characteristics
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Analysis of Overload of a Charge-Pump PLL
Eun-Chang CHOI Bhum-Cheol LEE Hee-Young JUNG Kwon-Chul PARK 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1997/12/25
Vol. E80-B  No. 12 ; pp. 1770-1779
Type of Manuscript:  PAPER
Category: Communication Device and Circuit
Keyword: 
charge-pumpoverloadstabilityphase-locked loop (PLL)
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Compact Realization of Phase-Locked Loop Using Digital Control
Masanori IZUMIKAWA Masakazu YAMASHINA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/04/25
Vol. E80-C  No. 4 ; pp. 544-549
Type of Manuscript:  Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Category: 
Keyword: 
phase-locked loop (PLL)digital controlD/A converter
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Design of a 3.2 GHz 50 mW 0.5 µm GaAs PLL-Based Clock Generator with 1 V Power Supply
Tadayoshi ENOMOTO Toshiyuki OKUYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12 ; pp. 1957-1965
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Processor Interfaces
Keyword: 
phase-locked loop (PLL)clock pulse generator (CG)voltage controlled ring oscillater (VCO)VCO gainGaAsMESFETDCFL circuitpull-in frequencypull-in rangepull-in timelock rangelock timelocked state
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