Keyword : phase resolution

A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution
Chang-Kyung SEONG Seung-Woo LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/01/01
Vol. E90-C  No. 1 ; pp. 165-170
Type of Manuscript:  PAPER
Category: Electronic Circuits
dual-loop clock and data recovery (CDR)phase interpolatorphase resolution
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All Digital DLL with Three Phase Tuning Stages
Jin-Ho CHOI Jin-Ku KANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/06/01
Vol. E87-A  No. 6 ; pp. 1305-1309
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003))
all digital DLLphase resolutionphase errorCMOS
 Summary | Full Text:PDF