Keyword : phase locked loop (PLL)


A 60 GHz CMOS Transceiver IC for a Short-Range Wireless System with Amplitude/Phase Imbalance Cancellation Technique
Koji TAKINAMI Junji SATO Takahiro SHIMA Mitsuhiro IWAMOTO Taiji AKIZUKI Masashi KOBAYASHI Masaki KANEMARU Yohei MORISHITA Ryo KITAMURA Takayuki TSUKIZAWA Koichi MIZUNO Noriaki SAITO Kazuaki TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/10/01
Vol. E95-C  No. 10 ; pp. 1598-1609
Type of Manuscript:  Special Section PAPER (Special Section on Recent Progress in Microwave and Millimeter-Wave Technologies)
Category: 
Keyword: 
CMOSmillimeter-wavedirect conversionamplitude/phase imbalancephase locked loop (PLL)injection locked frequency dividercalibrationpush-push voltage controlled oscillator60 GHz
 Summary | Full Text:PDF

A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting
Pao-Lung CHEN Chen-Yi LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3554-3563
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Circuit
Keyword: 
frequency synthesizerdynamic frequency counting (DFC)digitally-controlled varactors (DCV)digitally-controlled oscillator (DCO)dynamic element matching (DEM)phase locked loop (PLL)
 Summary | Full Text:PDF