Keyword : phase detector

Deadzone-Minimized Systematic Offset-Free Phase Detectors
Young-Sang KIM Yunjae SUH Hong-June PARK Jae-Yoon SIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1525-1528
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
phase detector, phase offset, deadzone, multiphase generation, delay-locked loop, phase-locked loop, 
 Summary | Full Text:PDF
A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector
Ching-Yuan YANG Yu LEE Cheng-Hsing LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 746-752
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: 
Keyword: 
phase-locked loop, phase synchronization, clock and data recovery, phase detector, 
 Summary | Full Text:PDF
A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector
Jae-Wook LEE Cheon-O LEE Woo-Young CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2003/07/01
Vol. E86-B  No. 7 ; pp. 2186-2189
Type of Manuscript:  LETTER
Category: Communication Devices/Circuits
Keyword: 
clock and data recovery, phase detector, phase locked loop, 
 Summary | Full Text:PDF
A New Phase Detector Scheme for Reducing Jitter in Clock Recovery Circuits
Kang-Yoon LEE Deog-Kyoon JEONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/02/01
Vol. E86-C  No. 2 ; pp. 224-228
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
phase detector, jitter, clock recovery, PLL, 
 Summary | Full Text:PDF
A Polarity Decision Carrier Recovery Algorithm Using Selected Symbols for High Order QAM
Kiyun KIM Hyungjin CHOI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2000/11/25
Vol. E83-B  No. 11 ; pp. 2542-2544
Type of Manuscript:  LETTER
Category: Wireless Communication Technology
Keyword: 
carrier recovery, QAM, phase detector, 
 Summary | Full Text:PDF
Computer Simulation of Jitter Characteristics of PLL for Arbitrary Data and Jitter Patterns
Kenichi NAKASHI Hiroyuki SHIRAHAMA Kenji TANIGUCHI Osamu TSUKAHARA Tohru EZAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6 ; pp. 977-984
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93))
Category: Analog Circuits and Signal Processing
Keyword: 
PLL, jitter, time-domain simulation, phase detector, NRZ, retiming, 
 Summary | Full Text:PDF