Keyword : path-status graph

High Quality Delay Test Generation Based on Multiple-Threshold Gate-Delay Fault Model
Michinobu NAKAO Yoshikazu KIYOSHIGE Yasuo SATO Kazumi HATAYAMA Satoshi FUKUMOTO Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1506-1514
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
delay testingpath selectionfault simulationtest generationpath-status graph
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