Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D
No. 10 ;
pp. 1506-1514
Type of Manuscript:
Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Test and Diagnosis for Timing Faults
Keyword:
delay testing, path selection, fault simulation, test generation, path-status graph, |
