Keyword : path delay fault


Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9 ; pp. 2295-2303
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
two-rail logic circuitpath delay faulttestabilityfunctional sensitizabilityover-testing
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On-Line Pruning of ZBDD for Path Delay Fault Coverage Calculation
Fatih KOCAN Mehmet H. GUNES Atakan KURT 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1381-1388
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Programmable Logic, VLSI, CAD and Layout
Keyword: 
path delay faultsimulationon-line pruningZBDD
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On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis
Masayasu FUKUNAGA Seiji KAJIHARA Sadami TAKEOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1671-1677
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
path delay faultuntestable pathpotentially testable pathfault efficiency
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Evaluation of Delay Testing Based on Path Selection
Masayasu FUKUNAGA Seiji KAJIHARA Sadami TAKEOKA Shinichi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3208-3210
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Test Generation
Keyword: 
delay testingpath delay faultpath selectionuntestable path
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