Keyword : pass-transistor network


Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit
Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/10/01
Vol. E85-C  No. 10 ; pp. 1814-1823
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
interconnection problempass-transistor networkfunctional pass gatemultiple-valued logiccontent-addressable memory
 Summary | Full Text:PDF

Dynamic-Storage-Based Logic-in-Memory Circuit and Its Application to a Fine-Grain Pipelined System
Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 288-296
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
pass-transistor networkfunctional pass gateprecharge-evaluate logicmultipliersigned-digit adder
 Summary | Full Text:PDF

Multiple-Valued Logic-in-Memory VLSI Architecture Based on Floating-Gate-MOS Pass-Transistor Logic
Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1662-1668
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Non-Binary Architectures
Keyword: 
pass-transistor networkfloating-gate MOS transistorlogic-in-memory structureManhattan distanceflash EEPROM technologyfour-valued full adder
 Summary | Full Text:PDF