IEICE Trans

Keyword : parasitic capacitance

An AM-PM Noise Mitigation Technique in Class-C VCO Kento KIMURA Aravind THARAYIL NARAYANAN Kenichi OKADA Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2015/12/01 Vol. E98-C No. 12 ; pp. 1161-1170 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: VCO, Class-C, AM-PM conversion, parasitic capacitance, cross coupled pair, noise sensitivity,
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State-Dependence of On-Chip Power Distribution Network Capacitance Koh YAMANAGA Shiho HAGIWARA Ryo TAKAHASHI Kazuya MASU Takashi SATO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2014/01/01 Vol. E97-C No. 1 ; pp. 77-84 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: CMOS logic circuit, state-dependent capacitance model, capacitance measurement, PDN-capacitance, parasitic capacitance,
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On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch Jinmyoung KIM Toru NAKURA Hidehiro TAKATA Koichiro ISHIBASHI Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 ; pp. 511-519 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: power supply noise, resonance, parasitic capacitance, sleep block, DVS, power gating,
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Importance and Limitations of Modeling Parasitic Capacitance between Package and PCB for Power Bus Noise and Radiation Umberto PAOLETTI Takashi HISAKADO Osami WADA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2009/06/01 Vol. E92-B No. 6 ; pp. 1937-1944 Type of Manuscript: Special Section PAPER (Special Section on 3rd Pan-Pacific EMC Joint Meeting -- PPEMC'08--) Category: Keyword: common mode, parasitic capacitance, package, simultaneous switching noise,
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Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation Toshiki KANAMOTO Shigekiyo AKUTSU Tamiyo NAKABAYASHI Takahiro ICHINOMIYA Koutaro HACHIYA Atsushi KUROKAWA Hiroshi ISHIKAWA Sakae MUROMOTO Hiroyuki KOBAYASHI Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 ; pp. 3666-3670 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: interconnect, delay variation, parasitic capacitance, SoC,
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The Structures of CPW PHEMT's for Applications of Millimeter-Waves Byeong-Ok LIM Tae-Shin KANG Bok-Hyung LEE Mun-Kyo LEE Jin-Koo RHEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/06/01 Vol. E87-A No. 6 ; pp. 1323-1329 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003)) Category: Keyword: CPW, CPW PHEMT, air-bridge interconnection, small signal model, parasitic capacitance,
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Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays Sadahiro TANI Yoshihiro UCHIDA Makoto FURUIE Shuji TSUKIYAMA BuYeol LEE Shuji NISHI Yasushi KUBOTA Isao SHIRAKAWA Shigeki IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 ; pp. 2923-2932 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: interconnect, LCD, parasitic capacitance, signal integrity, circuit simulation,
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A Three-Mode Switched-LNA Using a Low Parasitic Capacitance MOSFET Switch Toshifumi NAKATANI Koichi OGAWA Junji ITOH Ikuo IMANISHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/06/01 Vol. E86-C No. 6 ; pp. 1032-1040 Type of Manuscript: Special Section PAPER (Special Issue on Devices and Circuits for Next Generation Multi-Media Communication Systems) Category: Keyword: low noise amplifier, noise figure, MOSFET switch, parasitic capacitance, 3rd-order intercept point, dissipation power, cross-modulation,
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Evaluation of Fixed Charge and Interface Trap Densities in SIMOX Wafers and Their Effects on Device Characteristics Shoichi MASUI Tatsuo NAKAJIMA Keisuke KAWAMURA Takayuki YANO Isao HAMAGUCHI Masaharu TACHIMORI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/09/25 Vol. E78-C No. 9 ; pp. 1263-1272 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SOI, fixed oxide charge, interface trap, parasitic capacitance, subthreshold slope,
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The Effect of Internal Parasitic Capacitances in Series-Connected MOS Structure Sang Heon LEE Song Bai PARK Kyu Ho PARK
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/01/25 Vol. E78-A No. 1 ; pp. 142-145 Type of Manuscript: LETTER Category: VLSI Design Technology Keyword: computer aided design (CAD), modeling and simulation, parasitic capacitance, delay model, series-connected MOS structure,
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Effects of Line Resistance and Parasitic Capacitance on Transmittance Distribution in TFT-LCDs Kikuo ONO Takeshi TANAKA Jun OHIDA Junichi OHWADA Nobutake KONISHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/01/25 Vol. E75-C No. 1 ; pp. 93-100 Type of Manuscript: PAPER Category: Electronic Displays Keyword: thin film transistor, liquid crystal display, parasitic capacitance, resistance, simulation,
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