Keyword : parallelism

View Priority Based Threads Allocation and Binary Search Oriented Reweight for GPU Accelerated Real-Time 3D Ball Tracking
Yilin HOU Ziwei DENG Xina CHENG Takeshi IKENAGA 
Publication Date: 2018/12/01
Vol. E101-D  No. 12 ; pp. 3190-3198
Type of Manuscript:  PAPER
Category: Image Recognition, Computer Vision
real-timeGraphics Processing Unit (GPU)parallelismthread allocationparticle filterball tracking
 Summary | Full Text:PDF(2.1MB)

An Efficient Parallel Coding Scheme in Erasure-Coded Storage Systems
Wenrui DONG Guangming LIU 
Publication Date: 2018/03/01
Vol. E101-D  No. 3 ; pp. 627-643
Type of Manuscript:  PAPER
Category: Computer System
erasure codesstorageparallelismdata allocationmultiple threadsthread affinityperformance evaluation
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Tuning GridFTP Pipelining, Concurrency and Parallelism Based on Historical Data
Jangyoung KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/11/01
Vol. E97-D  No. 11 ; pp. 2963-2966
Type of Manuscript:  LETTER
Category: Information Network
big datathroughput optimizationthroughput estimationpipeliningconcurrencyparallelism
 Summary | Full Text:PDF(342KB)

A 64 Cycles/MB, Luma-Chroma Parallelized H.264/AVC Deblocking Filter for 4 K2 K Applications
Weiwei SHEN Yibo FAN Xiaoyang ZENG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 441-446
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
H.264/AVCdeblocking filterpipelineparallelism4 K2 K
 Summary | Full Text:PDF(1.8MB)

Generic Permutation Network for QC-LDPC Decoder
Xiao PENG Xiongxin ZHAO Zhixiang CHEN Fumiaki MAEHARA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2551-2559
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
LDPC decoderreconfigurablepermutation networkparallelism
 Summary | Full Text:PDF(1.2MB)

Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images
Wujian ZHANG Runde ZHOU Tsunehachi ISHITANI Ryota KASAI Toshio KONDO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/03/01
Vol. E84-C  No. 3 ; pp. 399-409
Type of Manuscript:  PAPER
Category: Integrated Electronics
motion estimationlow bit resolutionVLSI architectureparallelismlow power
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