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| Keyword : parallel
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A 48 Cycles/MB H.264/AVC Deblocking Filter Architecture for Ultra High Definition Applications
Dajiang ZHOU Jinjia ZHOU Jiayi ZHU Satoshi GOTO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A
No. 12 ;
pp. 3203-3210
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword:
H.264/AVC, parallel, deblocking, ultra high resolution, QFHD, | | | Summary | Full Text:PDF | |
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A 10-b 300-MHz Interpolated-Parallel A/D Converter
Hiroshi KIMURA Akira MATSUZAWA Takashi NAKAMURA Shigeki SAWADA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 1993/05/25
Vol. E76-C
No. 5 ;
pp. 778-786
Type of Manuscript:
Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))
Category:
Keyword:
A/D converter, parallel, interpolation, high speed, high resolution, linearity, circuit, bipolar, submicrometer, folding, encoder, logic, | | | Summary | Full Text:PDF | |
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