Keyword : parallel processor


Media Processing LSI Architectures for Automotives -- Challenges and Future Trends --
Ichiro KURODA Shorin KYO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 1850-1857
Type of Manuscript:  INVITED PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: 
Keyword: 
car electronicsimage recognitioncomputer vision3D graphicsparallel processorgraphics processing unit (GPU)
 Summary | Full Text:PDF(666.2KB)

A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications
Shorin KYO Takuya KOGA Shin'ichiro OKAZAKI Ichiro KURODA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/01/01
Vol. E87-D  No. 1 ; pp. 136-145
Type of Manuscript:  Special Section PAPER (Special Section on Machine Vision Applications)
Category: Processor
Keyword: 
video recognitionimage processingparallel processorvideo-based driver support systemsITSparallel language
 Summary | Full Text:PDF(4.7MB)

Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
Kazutoshi KOBAYASHI Masanao YAMAOKA Yukifumi KOBAYASHI Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2400-2408
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
VLSIfunctional memoryDRAMparallel processorblock matching
 Summary | Full Text:PDF(868.6KB)

A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization
Kazutoshi KOBAYASHI Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2 ; pp. 215-222
Type of Manuscript:  Special Section PAPER (Special Section on VLSI for Digital Signal Processing)
Category: 
Keyword: 
vector quantizationfunctional memoryparallel processorlow-rate image compressionnoise robustnessMSHVQ
 Summary | Full Text:PDF(665.6KB)

An LSI for Low Bit-Rate Image Compression Using Vector Quantization
Kazutoshi KOBAYASHI Noritsugu NAKAMURA Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5 ; pp. 718-724
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
parallel processormemory-basedvector quantizationlow bit-rate image compressionlow powerSIMD
 Summary | Full Text:PDF(748.2KB)

A Memory-Based Parallel Processor for Vector Quantization: FMPP-VQ
Kazutoshi KOBAYASHI Masayoshi KINOSHITA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7 ; pp. 970-975
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Multi Processors
Keyword: 
parallel processormemory-basevector quantizationlow bit-rate image compressionSIMD
 Summary | Full Text:PDF(632KB)

Single-Board SIMD Processors Using Gate-Array LSIs for Parallel Processing
Toshio KONDO Yoshimasa KIMURA Noboru SONEHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/12/25
Vol. E76-C  No. 12 ; pp. 1827-1834
Type of Manuscript:  Special Section PAPER (Special Issue on ASICs for Automotive Electronics)
Category: 
Keyword: 
parallel processorSIMDgate-arraytree network
 Summary | Full Text:PDF(689KB)

A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture
Kazutoshi KOBAYASHI Keikichi TAMARU Hiroto YASUURA Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/07/25
Vol. E76-C  No. 7 ; pp. 1151-1158
Type of Manuscript:  Special Section PAPER (Special Issue on New Architecture LSIs)
Category: Memory-Based Parallel Processor Architectures
Keyword: 
parallel processormemory-based simple structurelogical and arithmetic operations
 Summary | Full Text:PDF(734.9KB)