IEICE Trans

Keyword : parallel processor

Media Processing LSI Architectures for Automotives -- Challenges and Future Trends -- Ichiro KURODA Shorin KYO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 ; pp. 1850-1857 Type of Manuscript: INVITED PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Keyword: car electronics, image recognition, computer vision, 3D graphics, parallel processor, graphics processing unit (GPU),
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A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications Shorin KYO Takuya KOGA Shin'ichiro OKAZAKI Ichiro KURODA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/01/01 Vol. E87-D No. 1 ; pp. 136-145 Type of Manuscript: Special Section PAPER (Special Section on Machine Vision Applications) Category: Processor Keyword: video recognition, image processing, parallel processor, video-based driver support systems, ITS, parallel language,
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Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition Kazutoshi KOBAYASHI Masanao YAMAOKA Yukifumi KOBAYASHI Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/12/25 Vol. E83-A No. 12 ; pp. 2400-2408 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: VLSI, functional memory, DRAM, parallel processor, block matching,
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A Real-Time Low-Rate Video Compression Algorithm Using Multi-Stage Hierarchical Vector Quantization Kazutoshi KOBAYASHI Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/25 Vol. E82-A No. 2 ; pp. 215-222 Type of Manuscript: Special Section PAPER (Special Section on VLSI for Digital Signal Processing) Category: Keyword: vector quantization, functional memory, parallel processor, low-rate image compression, noise robustness, MSHVQ,
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An LSI for Low Bit-Rate Image Compression Using Vector Quantization Kazutoshi KOBAYASHI Noritsugu NAKAMURA Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/25 Vol. E81-C No. 5 ; pp. 718-724 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: Keyword: parallel processor, memory-based, vector quantization, low bit-rate image compression, low power, SIMD,
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A Memory-Based Parallel Processor for Vector Quantization: FMPP-VQ Kazutoshi KOBAYASHI Masayoshi KINOSHITA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/25 Vol. E80-C No. 7 ; pp. 970-975 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Multi Processors Keyword: parallel processor, memory-base, vector quantization, low bit-rate image compression, SIMD,
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Single-Board SIMD Processors Using Gate-Array LSIs for Parallel Processing Toshio KONDO Yoshimasa KIMURA Noboru SONEHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/12/25 Vol. E76-C No. 12 ; pp. 1827-1834 Type of Manuscript: Special Section PAPER (Special Issue on ASICs for Automotive Electronics) Category: Keyword: parallel processor, SIMD, gate-array, tree network,
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A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture Kazutoshi KOBAYASHI Keikichi TAMARU Hiroto YASUURA Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/07/25 Vol. E76-C No. 7 ; pp. 1151-1158 Type of Manuscript: Special Section PAPER (Special Issue on New Architecture LSIs) Category: Memory-Based Parallel Processor Architectures Keyword: parallel processor, memory-based simple structure, logical and arithmetic operations,
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