Keyword : parallel architecture


Design of q-Parallel LFSR-Based Syndrome Generator
Seung-Youl KIM Kyoung-Rok CHO Je-Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7 ; pp. 594-596
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
error control codeparallel architectureLFSRBCH
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A 1.5 Gb/s Highly Parallel Turbo Decoder for 3GPP LTE/LTE-Advanced
Yun CHEN Xubin CHEN Zhiyuan GUO Xiaoyang ZENG Defeng HUANG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2013/05/01
Vol. E96-B  No. 5 ; pp. 1211-1214
Type of Manuscript:  LETTER
Category: Fundamental Theories for Communications
Keyword: 
turbo decoderparallel architectureLTE4G
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A Parallel Timing Adjustment Algorithm for High Speed Wireless Burst Communication
Xiaofeng WAN Yu ZHANG Zhixing YANG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2011/05/01
Vol. E94-B  No. 5 ; pp. 1472-1475
Type of Manuscript:  LETTER
Category: Wireless Communication Technologies
Keyword: 
Gardner algorithmtiming adjustmentburst communicationparallel architecture
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A Low-Cost Continuous-Flow Parallel Memory-Based FFT Processor for UWB Applications
Chin-Long WEY Shin-Yo LIN Hsu-Sheng WANG Hung-Lieh CHEN Chun-Ming HUANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/01/01
Vol. E94-A  No. 1 ; pp. 315-323
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
fast Fourier transform (FFT)orthogonal frequency division multiplexing (OFDM)ultra-wideband (UWB)continuous flowparallel architecture
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Parallel Architecture for 2-D Discrete Wavelet Transform with Low Energy Consumption
Nozomi ISHIHARA Koki ABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/08/01
Vol. E91-A  No. 8 ; pp. 2068-2075
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
DWTsignal processingparallel architectureefficient memory accessburst accessASIC
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Design of Optimal Array Processors for Two-Step Division-Free Gaussian Elimination
Shietung PENG Stanislav G. SEDUKHIN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/12/25
Vol. E82-D  No. 12 ; pp. 1503-1511
Type of Manuscript:  PAPER
Category: Algorithm and Computational Complexity
Keyword: 
linear systemparallel algorithmparallel architecturesystolic array processors
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A Fixed-Point DSP (MDSP) Chip for Portable Multimedia
Soohwan ONG Myung H. SUNWOO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/06/25
Vol. E82-A  No. 6 ; pp. 939-944
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98))
Category: 
Keyword: 
SIMDvector processingparallel architecturevideo signal processingdigital signal processing
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Parallel Architecture for Generalized LFSR in LSI Built-In Self Testing
Tomoko K. MATSUSHIMA Toshiyasu MATSUSHIMA Shigeichi HIRASAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6 ; pp. 1252-1261
Type of Manuscript:  PAPER
Category: Reliability and Fault Analysis
Keyword: 
built-in self testsignature analysislinear feedback shift register aliasing probabilityparallel architecture
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A Parallel Hardware Architecture for Accelerating α-β Game Tree Search
Yi-Fan KE Tai-Ming PARNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/09/25
Vol. E79-D  No. 9 ; pp. 1232-1240
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
parallel searchparallel architecturecomputer chessα-β algorithm
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Parallel Encoder and Decoder Architecture for Cyclic Codes
Tomoko K. MATSUSHIMA Toshiyasu MATSUSHIMA Shigeichi HIRASAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/09/25
Vol. E79-A  No. 9 ; pp. 1313-1323
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
error correctioncyclic codeparallel architecturecircuit designencoderdecoder
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A Design of Pipelined Architecture for Hierarchical Block-Matching Algorithm
Hyung Chul KIM Seung Ryoul MAENG Jung Wan CHO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/05/25
Vol. E78-D  No. 5 ; pp. 586-595
Type of Manuscript:  PAPER
Category: Image Processing, Computer Graphics and Pattern Recognition
Keyword: 
parallel architecturemotion estimation algorithmvideo coding
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Packing Sequential Stretches in the MDFM
Paulo LORENZO Munehiro GOTO Arthur J. CATTO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/04/25
Vol. E78-D  No. 4 ; pp. 345-354
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
dataflow modelManchester Dataflow Machineparallel architecturepartitioning of parallel programstask packing
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RHINE: Reconfigurable Multiprocessor System for Video CODEC
Yoshinori TAKEUCHI Zhao-Chen HUANG Masatomo SAEKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6 ; pp. 947-956
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Methods and Circuits for Signal Processing
Keyword: 
parallel processingload balancingvideo CODECparallel architecturereconfigurable architecture
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