Keyword : parallel LDPC decoder architecture

Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule
Kazunori SHIMIZU Tatsuyuki ISHIKAWA Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3602-3612
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
low-density parity-check codesparallel LDPC decoder architecturemessage-passing algorithmFIFO-based buffering
 Summary | Full Text:PDF(1017.1KB)