Keyword : overlap resolution number system

Optimization and Verification of Current-Mode Multiple-Valued Digit ORNS Arithmetic Circuits
Motoi INABA Koichi TANNO Hiroki TAMURA Okihiko ISHIZUKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2073-2079
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: Multiple-Valued VLSI Technology
multiple-valued logicoverlap resolution number systemcurrent-mode circuitweak-inversion region
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