Keyword : over-testing


Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits
Kazuteru NAMBA Hideo ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9 ; pp. 2295-2303
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
two-rail logic circuitpath delay faulttestabilityfunctional sensitizabilityover-testing
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