Keyword : open faults


SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines
Jun YAMASHITA Hiroyuki YOTSUYANAGI Masaki HASHIZUME Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2561-2567
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
open faultsadjacent linestest pattern generationcoupling capacitanceSAT-based ATPG
 Summary | Full Text:PDF(590.4KB)

Ramp Voltage Testing for Detecting Interconnect Open Faults
Yukiya MIURA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 700-705
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Defect-Based Testing
Keyword: 
CMOS circuitsdefect oriented testingopen faultsramp voltage
 Summary | Full Text:PDF(371.1KB)

A Learning Algorithm for Fault Tolerant Feedforward Neural Networks
Nait Charif HAMMADI Hideo ITO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/01/25
Vol. E80-D  No. 1 ; pp. 21-27
Type of Manuscript:  Special Section PAPER (Special Issue on Fault-Tolerant Computing)
Category: Redundancy Techniques
Keyword: 
feedforward neural networklearning algorithmrelevance of synaptic weightsessential linkopen faults
 Summary | Full Text:PDF(528.2KB)