Keyword : non-scan design


A Design Scheme for Delay Testing of Controllers Using State Transition Information
Tsuyoshi IWAGAKI Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3200-3207
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
controllerdelay faultnon-scan designinvalid test state and transition generatorat-speed test
 Summary | Full Text:PDF(463.8KB)

High-Level Synthesis for Weakly Testable Data Paths
Michiko INOUE Kenji NODA Takeshi HIGASHIMURA Toshimitsu MASUZAWA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 645-653
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Test Synthesis
Keyword: 
high-level synthesistestabilitysequential ATPGnon-scan design
 Summary | Full Text:PDF(894.6KB)