Keyword : non-overlap clock signal


Test Structure for Characterizing Capacitance Matrix of Multi-Layer Interconnects in VLSI
Tetsuhisa MIDO Hiroshi ITO Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/04/25
Vol. E82-C  No. 4 ; pp. 570-575
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: 
Keyword: 
test structurecapacitance matrixVLSI interconnectionshift registersnon-overlap clock signalsub-femto-farad measurement
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