Keyword : non-binary


Hybrid Message-Passing Algorithm and Architecture for Decoding Cyclic Non-binary LDPC Codes
Yichao LU Gang HE Guifen TIAN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2652-2659
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
Belief propagation algorithmiterative majority-logic decodinglow-density parity-check codesnon-binaryVLSI
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SAR ADC Algorithm with Redundancy and Digital Error Correction
Tomohiko OGAWA Haruo KOBAYASHI Yosuke TAKAHASHI Nobukazu TAKAI Masao HOTTA Hao SAN Tatsuji MATSUURA Akira ABE Katsuyoshi YAGI Toshihiko MORI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/02/01
Vol. E93-A  No. 2 ; pp. 415-423
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
SAR ADCdigital error correctionnon-binaryredundancy
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Pseudo Floating Point Representation for Non-binary Turbo Decoder Extrinsic Information Memory Reduction
Sook Min PARK Jaeyoung KWAK Do-Sik YOO Kwyro LEE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2007/11/01
Vol. E90-B  No. 11 ; pp. 3250-3254
Type of Manuscript:  LETTER
Category: Fundamental Theories for Communications
Keyword: 
non-binaryduo-binaryturbo codesextrinsic informationextrinsic memory
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